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References: <1442844542-16216-1-git-send-email-shmulik.ladkani@ravellosystems.com>
From: Jason Wang <jasowang@redhat.com>
Message-ID: <56037EF5.2000104@redhat.com>
Date: Thu, 24 Sep 2015 12:41:25 +0800
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Subject: Re: [Qemu-devel] [PATCH] vmxnet3: Support reading IMR registers on
 bar0
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To: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com>, qemu-devel@nongnu.org, Dmitry Fleytman <dmitry@daynix.com>
Cc: idan.brown@ravellosystems.com, Dana Rubin <dana.rubin@ravellosystems.com>



On 09/21/2015 10:09 PM, Shmulik Ladkani wrote:
> Instead of asserting, return the actual IMR register value.
> This is aligned with what's returned on ESXi.
>
> Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com>
> Tested-by: Dana Rubin <dana.rubin@ravellosystems.com>
>
> ---
>  hw/net/vmxnet3.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
> index 04159c8..97f19dc 100644
> --- a/hw/net/vmxnet3.c
> +++ b/hw/net/vmxnet3.c
> @@ -1165,9 +1165,13 @@ vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
>  static uint64_t
>  vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
>  {
> +    VMXNET3State *s = opaque;
> +
>      if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
>                          VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
> -        g_assert_not_reached();
> +        int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
> +                                         VMXNET3_REG_ALIGN);
> +        return s->interrupt_states[l].is_masked;
>      }
>  
>      VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);

Applied in https://github.com/jasowang/qemu/commits/net

Thanks.