From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZflFl-0002wS-8R for qemu-devel@nongnu.org; Sat, 26 Sep 2015 04:54:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZflFi-0005Um-2s for qemu-devel@nongnu.org; Sat, 26 Sep 2015 04:54:45 -0400 Received: from mail-la0-x22b.google.com ([2a00:1450:4010:c03::22b]:34549) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZflFh-0005Ub-Rz for qemu-devel@nongnu.org; Sat, 26 Sep 2015 04:54:42 -0400 Received: by lacdq2 with SMTP id dq2so64501418lac.1 for ; Sat, 26 Sep 2015 01:54:40 -0700 (PDT) Received: from [192.168.50.14] (89-70-144-114.dynamic.chello.pl. [89.70.144.114]) by smtp.gmail.com with ESMTPSA id f3sm843632lam.42.2015.09.26.01.54.39 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 26 Sep 2015 01:54:39 -0700 (PDT) From: "mar.krzeminski" Message-ID: <56065D4E.1060102@gmail.com> Date: Sat, 26 Sep 2015 10:54:38 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Triggering two arm processors from same interrupt (A9 and M3) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "qemu-devel@nongnu.org Developers" Hello again, My next question is still related with M3 and A9 board what I want to model. This time my peripheral has some interrupts that are connected both to A9 processor(gic), and M3 processor (nvic). Additionally those interrupts have same number. Currently I use only two in my model so I added to my device another interrupt that does the same, but are connected to different processor, and it seem that works. Is there any way that I can do it better - to connect one interrupt source to two receivers (A9 and M3)? Regards, Marcin