From: Richard Henderson <rth@twiddle.net>
To: Alvise Rigo <a.rigo@virtualopensystems.com>,
qemu-devel@nongnu.org, mttcg@greensocs.com
Cc: claudio.fontana@huawei.com, jani.kokkonen@huawei.com,
tech@virtualopensystems.com, alex.bennee@linaro.org,
pbonzini@redhat.com
Subject: Re: [Qemu-devel] [RFC v5 1/6] exec.c: Add new exclusive bitmap to ram_list
Date: Sat, 26 Sep 2015 10:15:20 -0700 [thread overview]
Message-ID: <5606D2A8.10501@twiddle.net> (raw)
In-Reply-To: <1443083566-10994-2-git-send-email-a.rigo@virtualopensystems.com>
On 09/24/2015 01:32 AM, Alvise Rigo wrote:
> + if (cpu == smp_cpus) {
> + if (smp_cpus >= EXCL_BITMAP_CELL_SZ) {
> + return bitmap[EXCL_BITMAP_GET_BYTE_OFFSET(addr)];
> + } else {
> + return bitmap[EXCL_BITMAP_GET_BYTE_OFFSET(addr)] &
> + ((1 << smp_cpus) - 1);
> + }
> + } else {
> + return bitmap[EXCL_BITMAP_GET_BYTE_OFFSET(addr)] & (1 << EXCL_IDX(cpu));
> + }
How can more than one cpu have the same address exclusively?
Isn't this scheme giving a whole page to a cpu, not a cacheline?
That's going to cause ll/sc conflicts where real hardware wouldn't.
r~
next prev parent reply other threads:[~2015-09-26 17:15 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-24 8:32 [Qemu-devel] [RFC v5 0/6] Slow-path for atomic instruction translation Alvise Rigo
2015-09-24 8:32 ` [Qemu-devel] [RFC v5 1/6] exec.c: Add new exclusive bitmap to ram_list Alvise Rigo
2015-09-26 17:15 ` Richard Henderson [this message]
2015-09-28 7:28 ` alvise rigo
2015-09-24 8:32 ` [Qemu-devel] [RFC v5 2/6] softmmu: Add new TLB_EXCL flag Alvise Rigo
2015-09-30 3:34 ` Richard Henderson
2015-09-30 9:24 ` alvise rigo
2015-09-30 11:09 ` Peter Maydell
2015-09-30 12:44 ` alvise rigo
2015-09-30 20:37 ` Richard Henderson
2015-09-24 8:32 ` [Qemu-devel] [RFC v5 3/6] softmmu: Add helpers for a new slowpath Alvise Rigo
2015-09-30 3:58 ` Richard Henderson
2015-09-30 9:46 ` alvise rigo
2015-09-30 20:42 ` Richard Henderson
2015-10-01 8:05 ` alvise rigo
2015-10-01 19:34 ` Richard Henderson
2015-09-24 8:32 ` [Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for excl accesses Alvise Rigo
2015-09-30 4:03 ` Richard Henderson
2015-09-30 10:16 ` alvise rigo
2015-09-24 8:32 ` [Qemu-devel] [RFC v5 5/6] configure: Use slow-path for atomic only when the softmmu is enabled Alvise Rigo
2015-09-30 4:05 ` Richard Henderson
2015-09-30 9:51 ` alvise rigo
2015-09-24 8:32 ` [Qemu-devel] [RFC v5 6/6] target-arm: translate: Use ld/st excl for atomic insns Alvise Rigo
2015-09-30 4:44 ` [Qemu-devel] [RFC v5 0/6] Slow-path for atomic instruction translation Paolo Bonzini
2015-09-30 8:14 ` alvise rigo
2015-09-30 13:20 ` Paolo Bonzini
2015-10-01 19:32 ` Emilio G. Cota
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