Re: [Qemu-devel] Triggering two arm processors from same interrupt (A9 and M3)

["mar.krzeminski" <mar.krzeminski@gmail.com>]

W dniu 26.09.2015 o 19:46, Peter Crosthwaite pisze:
> On Sat, Sep 26, 2015 at 9:08 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 26 September 2015 at 01:54, mar.krzeminski <mar.krzeminski@gmail.com> wrote:
>>> Hello again,
>>>
>>> My next question is still related with M3 and A9 board what I want to model.
>>> This time my peripheral has some interrupts that are connected both to A9
>>> processor(gic),
>>> and M3 processor (nvic). Additionally those interrupts have same number.
>>> Currently I use only two in my model so I added to my device another
>>> interrupt that does the same,
>>> but are connected to different processor, and it seem that works.
>>> Is there any way that I can do it better - to connect one interrupt source
>>> to two receivers (A9 and M3)?
>> This is what qemu_irq_split() is for.
Thanks, I even looked at this...
I am not used to open source or such complicated and undocumented code.
That is why dummy question like this came.

>>
> Yes this is right.
>
> There was the same problem with R5 and A9 double interrupt wiring, and
> to reduce the verbosity, I implemented automatic IRQ splitting in the
> qdev layer:
>
> https://github.com/Xilinx/qemu/blob/pub/2015.2.plnx/hw/core/qdev.c
>
> Line 461. Not sure what others think of this, but it would be nice to
> just double connect on machine level which is an intuitive API for
> this behaviour. It would make short work of bringing the zynqmp R5
> intc online.
>
> Regards,
> Peter
Thanks for this. It seem that my platform is similar to zynqmp.
Important difference for me is that I have simpler use cases - I need to 
boot
from M3, and that code starts two A9s or start linux in A9 using kernel 
parameter.
Current issue is that when my machine has enabled A9 and M3 (M3 became 
core 0),
and I want to boot linux kernel from this A9 core console is dead.
Anyway thanks for help.
>> -- PMM
>>