From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36331) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZgyTp-0001IV-Bc for qemu-devel@nongnu.org; Tue, 29 Sep 2015 13:14:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZgyTm-0006Ad-4l for qemu-devel@nongnu.org; Tue, 29 Sep 2015 13:14:17 -0400 Received: from mail-la0-x22c.google.com ([2a00:1450:4010:c03::22c]:35668) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZgyTl-00069s-Su for qemu-devel@nongnu.org; Tue, 29 Sep 2015 13:14:14 -0400 Received: by laer8 with SMTP id r8so16772307lae.2 for ; Tue, 29 Sep 2015 10:14:12 -0700 (PDT) References: <1443436639-6603-1-git-send-email-serge.fdrv@gmail.com> From: Sergey Fedorov Message-ID: <560AC6E2.6030005@gmail.com> Date: Tue, 29 Sep 2015 20:14:10 +0300 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-arm: Add MDCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers On 29.09.2015 12:33, Peter Maydell wrote: > On 28 September 2015 at 11:37, Sergey Fedorov wrote: >> Signed-off-by: Sergey Fedorov >> --- >> >> This patch is a prerequisite for a debug exception routing patch: >> https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03542.html >> >> target-arm/cpu-qom.h | 1 + >> target-arm/cpu.c | 1 + >> target-arm/cpu.h | 1 + >> target-arm/cpu64.c | 1 + >> target-arm/helper.c | 13 +++++++++++++ >> 5 files changed, 17 insertions(+) >> >> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h >> index 25fb1ce..d2b0769 100644 >> --- a/target-arm/cpu-qom.h >> +++ b/target-arm/cpu-qom.h >> @@ -167,6 +167,7 @@ typedef struct ARMCPU { >> uint64_t id_aa64mmfr0; >> uint64_t id_aa64mmfr1; >> uint32_t dbgdidr; >> + uint32_t mdcr; > This field should be named mdcr_el2 if we have it, but: > the reset value for this register is defined architecturally, > so we don't need to specify it per CPU. (It's "all 0s, except > the bottom field resets to the same value as PMCR.N". Strictly > speaking some fields are defined to be architecturally > unknown and so might differ per CPU, but only in ways which > a guest doesn't care about. We typically model these in > the same way for all guest CPUs in QEMU.) > We reset PMCR_EL0 to cpu->midr & 0xff000000. So if we want to reset MDCR_EL2.N with PMCR_EL0.N we should reset PMCR_EL0.N to the proper value somehow first. I think we could reset PMCR_EL0 with its own reset value from a dedicated ARMCPU structure field independent from MIDR_EL1 reset value. This makes sense considering that most of PMCR_EL0's fields are RO/UNKNOWN. What do you think? Best regards, Sergey