From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39032) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhTdH-0001V4-2p for qemu-devel@nongnu.org; Wed, 30 Sep 2015 22:30:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZhTdD-0003IA-St for qemu-devel@nongnu.org; Wed, 30 Sep 2015 22:30:07 -0400 Received: from mail-pa0-x230.google.com ([2607:f8b0:400e:c03::230]:36846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhTdD-0003Hb-NT for qemu-devel@nongnu.org; Wed, 30 Sep 2015 22:30:03 -0400 Received: by pablk4 with SMTP id lk4so57918674pab.3 for ; Wed, 30 Sep 2015 19:30:03 -0700 (PDT) Sender: Richard Henderson References: <1443448287-4433-1-git-send-email-gang.chen.5i5j@gmail.com> From: Richard Henderson Message-ID: <560C9AA0.6010206@twiddle.net> Date: Thu, 1 Oct 2015 12:29:52 +1000 MIME-Version: 1.0 In-Reply-To: <1443448287-4433-1-git-send-email-gang.chen.5i5j@gmail.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-tilegx: Check zero dest register for ld instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: gang.chen.5i5j@gmail.com, peter.maydell@linaro.org Cc: cmetcalf@ezchip.com, qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com On 09/28/2015 11:51 PM, gang.chen.5i5j@gmail.com wrote: > From: Chen Gang > > At present, qemu x86_64 host backend can not remove the related dummy > instructions. Even the worse, sometimes, it will generate the incorrect > instructions which will cause segment fault for prefetch_l3 instruction. > > Signed-off-by: Chen Gang > --- > target-tilegx/translate.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c > index 86da6b5..7232361 100644 > --- a/target-tilegx/translate.c > +++ b/target-tilegx/translate.c > @@ -620,7 +620,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext, > memop = MO_TEQ; > mnemonic = "ld"; > do_load: > - tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); > + if (dest != TILEGX_R_ZERO) { > + tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop); > + } This isn't right. Not all load instructions are nofault prefetches. r~ > break; > case OE_RR_X1(LDNA): > tcg_gen_andi_tl(tdest, tsrca, ~7); > @@ -1987,8 +1989,10 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) > memop = MO_TEQ; > mnemonic = "ld"; > do_load: > - tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), > - dc->mmuidx, memop); > + if (srcbdest != TILEGX_R_ZERO) { > + tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), > + dc->mmuidx, memop); > + } > qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, > reg_names[srcbdest], reg_names[srca]); > return TILEGX_EXCP_NONE; >