From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53894) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhjcy-0005Ge-Rr for qemu-devel@nongnu.org; Thu, 01 Oct 2015 15:34:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zhjcu-0007Ck-Ti for qemu-devel@nongnu.org; Thu, 01 Oct 2015 15:34:52 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:33855) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhjcu-0007CK-M9 for qemu-devel@nongnu.org; Thu, 01 Oct 2015 15:34:48 -0400 Received: by padhy16 with SMTP id hy16so83207956pad.1 for ; Thu, 01 Oct 2015 12:34:48 -0700 (PDT) Sender: Richard Henderson References: <1443083566-10994-1-git-send-email-a.rigo@virtualopensystems.com> <1443083566-10994-4-git-send-email-a.rigo@virtualopensystems.com> <560B5DE7.2040109@twiddle.net> <560C4942.700@twiddle.net> From: Richard Henderson Message-ID: <560D8ACB.3070809@twiddle.net> Date: Fri, 2 Oct 2015 05:34:35 +1000 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC v5 3/6] softmmu: Add helpers for a new slowpath List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: alvise rigo Cc: mttcg@greensocs.com, Claudio Fontana , QEMU Developers , Paolo Bonzini , Jani Kokkonen , VirtualOpenSystems Technical Team , =?UTF-8?Q?Alex_Benn=c3=a9e?= On 10/01/2015 06:05 PM, alvise rigo wrote: > On Wed, Sep 30, 2015 at 10:42 PM, Richard Henderson wrote: >> >> On 09/30/2015 07:46 PM, alvise rigo wrote: >>> >>> On Wed, Sep 30, 2015 at 5:58 AM, Richard Henderson wrote: >>>> >>>> Why would you need to indicate that another cpu has started an exclusive >>>> operation on this page? That seems definitely wrong. >>> >>> >>> The cpu_physical_memory_clear_excl_dirty() sets the flag to generate >>> the TLB entry with the EXCL flag. >> >> >> Yes, but surely the clearing of dirty on current_cpu is enough to cause the other cpus to see that they need to set TLB_EXCL when reloading their tlb entries. >> >> Why do you need to manipulate the *other* cpu's dirty bit? > > Because then we can assume that a cpu with the bit cleared has for > sure the TLB entries with the EXCL flag set for that specific page. > Moreover, knowing which cpus have the EXCL flag set allows to reduce > the flushing requests whenever a new LL is issued on the same page. Does it actually help, or is that a guess without numbers? r~