From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhjio-0005gv-Vb for qemu-devel@nongnu.org; Thu, 01 Oct 2015 15:41:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZhjiX-0002Dc-C1 for qemu-devel@nongnu.org; Thu, 01 Oct 2015 15:40:54 -0400 Received: from mail-pa0-x234.google.com ([2607:f8b0:400e:c03::234]:36643) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZhjiX-0002BV-2U for qemu-devel@nongnu.org; Thu, 01 Oct 2015 15:40:37 -0400 Received: by pablk4 with SMTP id lk4so82676282pab.3 for ; Thu, 01 Oct 2015 12:40:36 -0700 (PDT) Sender: Richard Henderson References: <1443697130-21431-1-git-send-email-james.hogan@imgtec.com> <1443697130-21431-6-git-send-email-james.hogan@imgtec.com> From: Richard Henderson Message-ID: <560D8C2A.705@twiddle.net> Date: Fri, 2 Oct 2015 05:40:26 +1000 MIME-Version: 1.0 In-Reply-To: <1443697130-21431-6-git-send-email-james.hogan@imgtec.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 5/6] tcg/mips: Support r6 multiply/divide encodings List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: James Hogan , qemu-devel@nongnu.org Cc: Leon Alrae , Aurelien Jarno On 10/01/2015 08:58 PM, James Hogan wrote: > MIPSr6 adds several new integer multiply, divide, and modulo > instructions, and removes several pre-r6 encodings, along with the HI/LO > registers which were the implicit operands of some of those > instructions. Update TCG to use the new instructions when built for r6. > > The new instructions actually map much more directly to the TCG ops, as > they only provide a single 32-bit half of the result and in a normal > general purpose register instead of HI or LO. > > The mulu2_i32 and muls2_i32 operations are no longer appropriate for r6, > so they are removed from the TCG opcode table. This is because they > would need to emit two separate host instructions anyway (for the high > and low half of the result), which TCG can arrange automatically for us > in the absense of mulu2_i32/muls2_i32 by splitting it into mul_i32 and > mul*h_i32 TCG ops. > > Signed-off-by: James Hogan > Cc: Richard Henderson > Cc: Aurelien Jarno > --- > Changes in v2: > - Use a common OPC_MUL definition. use_mips32_instructions will always > be 1 for MIPS r6 builds (Richard) > --- Reviewed-by: Richard Henderson r~