From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60855) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhq42-0006Sa-HZ for qemu-devel@nongnu.org; Thu, 01 Oct 2015 22:27:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zhq3y-0001ho-Hh for qemu-devel@nongnu.org; Thu, 01 Oct 2015 22:27:14 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:35546) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zhq3y-0001he-DG for qemu-devel@nongnu.org; Thu, 01 Oct 2015 22:27:10 -0400 Received: by pacfv12 with SMTP id fv12so94462714pac.2 for ; Thu, 01 Oct 2015 19:27:10 -0700 (PDT) Sender: Richard Henderson References: <1443703035-4433-1-git-send-email-gang.chen.5i5j@gmail.com> <560DD1AB.7080808@twiddle.net> <560DDE8D.8040202@ezchip.com> From: Richard Henderson Message-ID: <560DEB73.6020609@twiddle.net> Date: Fri, 2 Oct 2015 12:26:59 +1000 MIME-Version: 1.0 In-Reply-To: <560DDE8D.8040202@ezchip.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3] target-tilegx: Support iret instruction and related special registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Chris Metcalf , gang.chen.5i5j@gmail.com, peter.maydell@linaro.org Cc: qemu-devel@nongnu.org, xili_gchen_5257@hotmail.com On 10/02/2015 11:31 AM, Chris Metcalf wrote: > > It disables interrupts from being delivered. This means asynchronous > interrupts get deferred until ICS is set back to zero, and synchronous > interrupts (page fault, etc) cause a double-fault instead. ICS is automatically > set on entry to interrupt handlers, so the handler has time to acquire any > information about the interrupt from SPRs, and it is expected that ICS is > cleared as soon as possible. ICS can also be used before returning from > interrupts if you need to do something like adjust the interrupt mask prior to > returning. Which is all very well and good for supervisor mode... but what's it good for in user mode? I was about to quote you from 2012 (https://lkml.org/lkml/2012/3/30/994): > In general we want to avoid ever touching memory while within an > interrupt critical section, since the page fault path goes through > a different path from the hypervisor when in an interrupt critical > section, and we carefully decided with tilegx that we didn't need > to support this path in the kernel. Which implies that tilegx userland does nothing at all with ICS, and is in fact unsupported? r~