From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45284) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zi5xC-0001mE-9b for qemu-devel@nongnu.org; Fri, 02 Oct 2015 15:25:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zi5x8-0005PZ-ST for qemu-devel@nongnu.org; Fri, 02 Oct 2015 15:25:14 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:52920) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zi5x8-0005Oi-Jw for qemu-devel@nongnu.org; Fri, 02 Oct 2015 15:25:10 -0400 Message-ID: <560EDA12.1090307@codeaurora.org> Date: Fri, 02 Oct 2015 15:25:06 -0400 From: Christopher Covington MIME-Version: 1.0 References: <1430417667-4245-5-git-send-email-christopher.covington@linaro.org> <1443123824-26866-1-git-send-email-cov@codeaurora.org> <560A9B3B.3090407@codeaurora.org> <560EB472.1000901@codeaurora.org> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite , Peter Maydell Cc: Laurent Vivier , Paolo Bonzini , "qemu-devel@nongnu.org Developers" , Alistair Francis On 10/02/2015 01:25 PM, Peter Crosthwaite wrote: > On Fri, Oct 2, 2015 at 9:56 AM, Peter Maydell wrote: >> On 2 October 2015 at 17:44, Christopher Covington wrote: >>> I've sent out the CPI test case and while exercising it I noticed that >>> Laurent's patch fixed -icount. So my original goal has been accomplished. I'm >>> happy to rebase this patch if the authorities (Peter Maydell?) think using >>> cpu_get_ticks() is the right thing to do. Otherwise I'll probably try to move >>> on to support for the instructions event in the ARM PMU. >> >> Authority here is probably Peter Crosthwaite. I can produce an >> opinion but I'd have to go and research a bunch of stuff to do >> that, so I'm hoping to avoid it... > > So my idea here is the CPU input frequency should be a property of the CPU. > > Some experimental results confirm that the PMCCNTR on many common ARM > implementations is directly connected to the input clock and can be > relied on as a straight free-running counter. I think a genuine > instruction counter is something else Yes, the "genuine" instruction counter is something else. The instruction count is only relevant for folks trying to get deterministic execution by using the -icount option. QEMU TCG mode does not emulate a cycle-level input clock for the guest (the whole class of functional models skip this time-consuming step) but rather operates a block at a time. By doing a little extra, I think it also interpolates the exact instruction count. Specifying a fixed IPC = n is the most sensible way of deterministically calculating a PMCCNTR_EL0 value that I know of. The -icount option allows users to choose such deterministic behavior. > and this timer should be independent of any core provider of cycle count. What, if anything, do you think should be hooked up to the core provider of cycle count? Christopher Covington -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project