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From: Christopher Covington <cov@codeaurora.org>
To: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Cc: Laurent Vivier <lvivier@redhat.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure
Date: Fri, 02 Oct 2015 16:48:58 -0400	[thread overview]
Message-ID: <560EEDBA.2020201@codeaurora.org> (raw)
In-Reply-To: <CAPokK=r3u3MGCv78X87vfX33DnN+s0GpJckV6T9Dp_hkko=Taw@mail.gmail.com>

On 10/02/2015 03:56 PM, Peter Crosthwaite wrote:
> On Fri, Oct 2, 2015 at 12:25 PM, Christopher Covington
> <cov@codeaurora.org> wrote:
>> On 10/02/2015 01:25 PM, Peter Crosthwaite wrote:
>>> On Fri, Oct 2, 2015 at 9:56 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
>>>> On 2 October 2015 at 17:44, Christopher Covington <cov@codeaurora.org> wrote:
>>>>> I've sent out the CPI test case and while exercising it I noticed that
>>>>> Laurent's patch fixed -icount. So my original goal has been accomplished. I'm
>>>>> happy to rebase this patch if the authorities (Peter Maydell?) think using
>>>>> cpu_get_ticks() is the right thing to do. Otherwise I'll probably try to move
>>>>> on to support for the instructions event in the ARM PMU.
>>>>
>>>> Authority here is probably Peter Crosthwaite. I can produce an
>>>> opinion but I'd have to go and research a bunch of stuff to do
>>>> that, so I'm hoping to avoid it...
>>>
>>> So my idea here is the CPU input frequency should be a property of the CPU.
>>>
>>> Some experimental results confirm that the PMCCNTR on many common ARM
>>> implementations is directly connected to the input clock and can be
>>> relied on as a straight free-running counter. I think a genuine
>>> instruction counter is something else
>>
>> Yes, the "genuine" instruction counter is something else. The instruction
>> count is only relevant for folks trying to get deterministic execution by
>> using the -icount option. QEMU TCG mode does not emulate a cycle-level input
>> clock for the guest (the whole class of functional models skip this
>> time-consuming step) but rather operates a block at a time. By doing a little
>> extra, I think it also interpolates the exact instruction count. Specifying a
>> fixed IPC = n is the most sensible way of deterministically calculating a
>> PMCCNTR_EL0 value that I know of. The -icount option allows users to choose
>> such deterministic behavior.
>>
>>> and this timer should be independent of any core provider of cycle count.
>>
>> What, if anything, do you think should be hooked up to the core provider of
>> cycle count?
> 
> Depends, Is this a virtual-machine only concept, or do you have
> something with a real-hardware analogue?

What I meant to ask was, do you see any reason for cpu_get_ticks() to exist?
If no architecture besides i386 wants to use it, perhaps the code should be
moved there.

Thanks,
Christopher Covington

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2015-10-02 20:49 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-30 18:14 [Qemu-devel] [RFC 1/5] arm64: Add PMINTENCLR_EL1 Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 2/5] arm64: Add PMOVSCLR_EL0 register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 3/5] arm64: Add PMUSERENR_EL0 register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 4/5] arm64: Unmask PMU bits in debug feature register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 5/5] arm: Simplify cycle counter Christopher Covington
2015-04-30 18:27   ` Peter Maydell
2015-04-30 21:33     ` Christopher Covington
2015-04-30 22:02       ` Peter Maydell
2015-05-04  9:54         ` Paolo Bonzini
2015-05-01  1:24   ` Peter Crosthwaite
2015-05-01 14:35     ` Christopher Covington
2015-05-06 14:05       ` Peter Crosthwaite
2015-05-06 15:38         ` Peter Maydell
2015-09-24 19:43   ` [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure Christopher Covington
2015-09-28 22:05     ` Alistair Francis
2015-09-29 14:07       ` Christopher Covington
2015-10-02 16:44         ` Christopher Covington
2015-10-02 16:56           ` Peter Maydell
2015-10-02 17:25             ` Peter Crosthwaite
2015-10-02 18:08               ` Peter Maydell
2015-10-02 18:14                 ` Peter Crosthwaite
2015-10-02 19:25               ` Christopher Covington
2015-10-02 19:56                 ` Peter Crosthwaite
2015-10-02 20:48                   ` Christopher Covington [this message]
2015-10-02 22:41                     ` Peter Maydell
2015-10-05 14:09                       ` Paolo Bonzini
2015-10-05 14:11                         ` Peter Maydell
2015-10-05 14:27                           ` Paolo Bonzini
2015-10-06 12:49                             ` Peter Maydell
2015-10-06 12:58                               ` Paolo Bonzini
2015-10-06 13:06                                 ` Peter Maydell
2015-10-06 13:10                                   ` Paolo Bonzini
2015-10-13 20:53     ` Peter Maydell
2015-10-14 12:10       ` Christopher Covington

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