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[83.11.13.124]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a68ae54b2sm74805966b.78.2024.10.18.03.24.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 18 Oct 2024 03:24:06 -0700 (PDT) Message-ID: <560a13ec-3954-45b6-a3b7-85c106b36eaf@linaro.org> Date: Fri, 18 Oct 2024 12:24:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] pcie: enable Extended tag field capability To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org, Marcel Apfelbaum References: <20241017-pcie-extend-v1-1-03eb1029f4ca@linaro.org> <20241017125724-mutt-send-email-mst@kernel.org> From: Marcin Juszkiewicz Content-Language: pl-PL, en-GB Organization: Linaro In-Reply-To: <20241017125724-mutt-send-email-mst@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=marcin.juszkiewicz@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org W dniu 17.10.2024 o 18:58, Michael S. Tsirkin pisze: >> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c >> index 4b2f0805c6..54c0f1ec67 100644 >> --- a/hw/pci/pcie.c >> +++ b/hw/pci/pcie.c >> @@ -86,7 +86,8 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) >> * Specification, Revision 1.1., or subsequent PCI Express Base >> * Specification revisions. >> */ >> - pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); >> + pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER | >> + PCI_EXP_DEVCAP_EXT_TAG); >> >> pci_set_long(exp_cap + PCI_EXP_LNKCAP, >> (port << PCI_EXP_LNKCAP_PN_SHIFT) | > > We can't change capabilities unconditionally. > It needs at least a machine type compat thing. Started looking and wonder how to pass it from MachineClass level down to pcie.c/pcie_cap_v1_fill() level. hw/arm/sbsa-ref.c (the machine I know best) has create_pcie() which allocates PCI_HOST_BRIDGE and then creates 2 pcie devices (default_nic (e1000e) and bochs-display gfx). If I add "pcie_uses_ext_tags = true" to SBSAMachineState then I need to have it stored in PCIBus structure so pci_create_simple() will know. This function would copy it into "dev" (PCIDevice) to make it pass to pcie_cap_v1_fill() function. But that's not right way because other PCIe devices are created in other places. Need to dig deeper.