* [Qemu-devel] [PATCH 1/3] target/sparc: convert to DisasJumpType
2018-02-15 23:17 [Qemu-devel] [PATCH 0/3] target/sparc: translator loop conversion Emilio G. Cota
@ 2018-02-15 23:17 ` Emilio G. Cota
2018-02-18 19:25 ` Richard Henderson
2018-02-15 23:17 ` [Qemu-devel] [PATCH 2/3] target/sparc: convert to DisasContextBase Emilio G. Cota
2018-02-15 23:17 ` [Qemu-devel] [PATCH 3/3] target/sparc: convert to TranslatorOps Emilio G. Cota
2 siblings, 1 reply; 7+ messages in thread
From: Emilio G. Cota @ 2018-02-15 23:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Artyom Tarasenko
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sparc/translate.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 71e0853..730e25d 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -30,6 +30,7 @@
#include "exec/helper-gen.h"
#include "trace-tcg.h"
+#include "exec/translator.h"
#include "exec/log.h"
#include "asi.h"
@@ -69,7 +70,7 @@ typedef struct DisasContext {
target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
- int is_br;
+ DisasJumpType is_jmp;
int mem_idx;
bool fpu_enabled;
bool address_mask_32bit;
@@ -995,7 +996,7 @@ static void gen_branch_a(DisasContext *dc, target_ulong pc1)
gen_set_label(l1);
gen_goto_tb(dc, 1, npc + 4, npc + 8);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
}
static void gen_branch_n(DisasContext *dc, target_ulong pc1)
@@ -1078,7 +1079,7 @@ static void gen_exception(DisasContext *dc, int which)
t = tcg_const_i32(which);
gen_helper_raise_exception(cpu_env, t);
tcg_temp_free_i32(t);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
}
static void gen_check_align(TCGv addr, int mask)
@@ -3346,7 +3347,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (cond == 8) {
/* An unconditional trap ends the TB. */
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
goto jmp_insn;
} else {
/* A conditional trap falls through to the next insn. */
@@ -4326,7 +4327,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
break;
case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
@@ -4335,7 +4336,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
break;
case 0xf: /* V9 sir, nop if user */
#if !defined(CONFIG_USER_ONLY)
@@ -4463,7 +4464,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
#endif
}
break;
@@ -4619,7 +4620,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
break;
case 1: // htstate
// XXX gen_op_wrhtstate();
@@ -5685,7 +5686,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else if (dc->npc == JUMP_PC) {
/* we can do a static jump */
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
} else {
dc->pc = dc->npc;
dc->npc = dc->npc + 4;
@@ -5747,6 +5748,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
pc_start = tb->pc;
dc->pc = pc_start;
last_pc = dc->pc;
+ dc->is_jmp = DISAS_NEXT;
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
@@ -5791,7 +5793,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
}
gen_helper_debug(cpu_env);
tcg_gen_exit_tb(0);
- dc->is_br = 1;
+ dc->is_jmp = DISAS_NORETURN;
goto exit_gen_loop;
}
@@ -5803,8 +5805,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
disas_sparc_insn(dc, insn);
- if (dc->is_br)
+ if (dc->is_jmp == DISAS_NORETURN) {
break;
+ }
/* if the next PC is different, we abort now */
if (dc->pc != (last_pc + 4))
break;
@@ -5825,7 +5828,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (!dc->is_br) {
+ if (dc->is_jmp != DISAS_NORETURN) {
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH 2/3] target/sparc: convert to DisasContextBase
2018-02-15 23:17 [Qemu-devel] [PATCH 0/3] target/sparc: translator loop conversion Emilio G. Cota
2018-02-15 23:17 ` [Qemu-devel] [PATCH 1/3] target/sparc: convert to DisasJumpType Emilio G. Cota
@ 2018-02-15 23:17 ` Emilio G. Cota
2018-02-18 19:25 ` Richard Henderson
2018-02-15 23:17 ` [Qemu-devel] [PATCH 3/3] target/sparc: convert to TranslatorOps Emilio G. Cota
2 siblings, 1 reply; 7+ messages in thread
From: Emilio G. Cota @ 2018-02-15 23:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Artyom Tarasenko
Notes:
- pc and npc are left unmodified, since they can point to out-of-TB
jump targets.
- Got rid of last_pc in gen_intermediate_code(), using base.pc_next
instead. Only update pc_next (1) on a breakpoint (so that tb->size
includes the insn), and (2) after reading the current instruction
from memory. This allows us to use base.pc_next in the BP check,
which is what the translator loop does.
- The original meaning of ctx.singlestep is
cs->singlestep_enabled || singlestep
, which required a little extra work since base.singlestep_enabled
only gets its value from cs->singlestep_enabled.
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sparc/translate.c | 90 +++++++++++++++++++++++++-----------------------
1 file changed, 47 insertions(+), 43 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 730e25d..da77a27 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -67,14 +67,13 @@ static TCGv_i64 cpu_fpr[TARGET_DPREGS];
#include "exec/gen-icount.h"
typedef struct DisasContext {
+ DisasContextBase base;
target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
- DisasJumpType is_jmp;
int mem_idx;
bool fpu_enabled;
bool address_mask_32bit;
- bool singlestep;
#ifndef CONFIG_USER_ONLY
bool supervisor;
#ifdef TARGET_SPARC64
@@ -83,7 +82,6 @@ typedef struct DisasContext {
#endif
uint32_t cc_op; /* current CC operation */
- struct TranslationBlock *tb;
sparc_def_t *def;
TCGv_i32 t32[3];
TCGv ttl[5];
@@ -342,13 +340,13 @@ static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
static inline bool use_goto_tb(DisasContext *s, target_ulong pc,
target_ulong npc)
{
- if (unlikely(s->singlestep)) {
+ if (unlikely(s->base.singlestep_enabled || singlestep)) {
return false;
}
#ifndef CONFIG_USER_ONLY
- return (pc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK) &&
- (npc & TARGET_PAGE_MASK) == (s->tb->pc & TARGET_PAGE_MASK);
+ return (pc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK) &&
+ (npc & TARGET_PAGE_MASK) == (s->base.tb->pc & TARGET_PAGE_MASK);
#else
return true;
#endif
@@ -362,7 +360,7 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
tcg_gen_goto_tb(tb_num);
tcg_gen_movi_tl(cpu_pc, pc);
tcg_gen_movi_tl(cpu_npc, npc);
- tcg_gen_exit_tb((uintptr_t)s->tb + tb_num);
+ tcg_gen_exit_tb((uintptr_t)s->base.tb + tb_num);
} else {
/* jump to another page: currently not optimized */
tcg_gen_movi_tl(cpu_pc, pc);
@@ -996,7 +994,7 @@ static void gen_branch_a(DisasContext *dc, target_ulong pc1)
gen_set_label(l1);
gen_goto_tb(dc, 1, npc + 4, npc + 8);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_branch_n(DisasContext *dc, target_ulong pc1)
@@ -1079,7 +1077,7 @@ static void gen_exception(DisasContext *dc, int which)
t = tcg_const_i32(which);
gen_helper_raise_exception(cpu_env, t);
tcg_temp_free_i32(t);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_check_align(TCGv addr, int mask)
@@ -2437,7 +2435,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
default:
/* ??? In theory, this should be raise DAE_invalid_asi.
But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */
- if (tb_cflags(dc->tb) & CF_PARALLEL) {
+ if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
} else {
TCGv_i32 r_asi = tcg_const_i32(da.asi);
@@ -3347,7 +3345,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
if (cond == 8) {
/* An unconditional trap ends the TB. */
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
goto jmp_insn;
} else {
/* A conditional trap falls through to the next insn. */
@@ -4327,7 +4325,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
@@ -4336,7 +4334,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 0xf: /* V9 sir, nop if user */
#if !defined(CONFIG_USER_ONLY)
@@ -4464,7 +4462,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
#endif
}
break;
@@ -4620,7 +4618,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
break;
case 1: // htstate
// XXX gen_op_wrhtstate();
@@ -5686,7 +5684,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
} else if (dc->npc == JUMP_PC) {
/* we can do a static jump */
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
} else {
dc->pc = dc->npc;
dc->npc = dc->npc + 4;
@@ -5737,25 +5735,26 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
{
CPUSPARCState *env = cs->env_ptr;
- target_ulong pc_start, last_pc;
DisasContext dc1, *dc = &dc1;
- int num_insns;
int max_insns;
unsigned int insn;
memset(dc, 0, sizeof(DisasContext));
- dc->tb = tb;
- pc_start = tb->pc;
- dc->pc = pc_start;
- last_pc = dc->pc;
- dc->is_jmp = DISAS_NEXT;
+ dc->base.tb = tb;
+ dc->base.pc_first = tb->pc;
+ dc->base.pc_next = tb->pc;
+ dc->base.is_jmp = DISAS_NEXT;
+ dc->base.num_insns = 0;
+ dc->base.singlestep_enabled = cs->singlestep_enabled;
+
+ dc->pc = dc->base.pc_first;
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
dc->def = &env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
- dc->singlestep = (cs->singlestep_enabled || singlestep);
+
#ifndef CONFIG_USER_ONLY
dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
#endif
@@ -5767,7 +5766,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
#endif
#endif
- num_insns = 0;
max_insns = tb_cflags(tb) & CF_COUNT_MASK;
if (max_insns == 0) {
max_insns = CF_COUNT_MASK;
@@ -5775,6 +5773,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS;
}
+ if (singlestep) {
+ max_insns = 1;
+ }
gen_tb_start(tb);
do {
@@ -5784,51 +5785,53 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
} else {
tcg_gen_insn_start(dc->pc, dc->npc);
}
- num_insns++;
- last_pc = dc->pc;
+ dc->base.num_insns++;
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
- if (dc->pc != pc_start) {
+ if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
+ if (dc->pc != dc->base.pc_first) {
save_state(dc);
}
gen_helper_debug(cpu_env);
tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_NORETURN;
+ dc->base.is_jmp = DISAS_NORETURN;
+ dc->base.pc_next += 4;
goto exit_gen_loop;
}
- if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
+ if (dc->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
gen_io_start();
}
insn = cpu_ldl_code(env, dc->pc);
+ dc->base.pc_next += 4;
disas_sparc_insn(dc, insn);
- if (dc->is_jmp == DISAS_NORETURN) {
+ if (dc->base.is_jmp == DISAS_NORETURN) {
break;
}
/* if the next PC is different, we abort now */
- if (dc->pc != (last_pc + 4))
+ if (dc->pc != dc->base.pc_next) {
break;
+ }
/* if we reach a page boundary, we stop generation so that the
PC of a TT_TFAULT exception is always in the right page */
if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
/* if single step mode, we generate only one instruction and
generate an exception */
- if (dc->singlestep) {
+ if (dc->base.singlestep_enabled) {
break;
}
} while (!tcg_op_buf_full() &&
- (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
- num_insns < max_insns);
+ (dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) &&
+ dc->base.num_insns < max_insns);
exit_gen_loop:
if (tb_cflags(tb) & CF_LAST_IO) {
gen_io_end();
}
- if (dc->is_jmp != DISAS_NORETURN) {
+ if (dc->base.is_jmp != DISAS_NORETURN) {
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
@@ -5841,18 +5844,19 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
tcg_gen_exit_tb(0);
}
}
- gen_tb_end(tb, num_insns);
+ gen_tb_end(tb, dc->base.num_insns);
- tb->size = last_pc + 4 - pc_start;
- tb->icount = num_insns;
+ tb->size = dc->base.pc_next - dc->base.pc_first;
+ tb->icount = dc->base.num_insns;
#ifdef DEBUG_DISAS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
+ && qemu_log_in_addr_range(dc->base.pc_first)) {
qemu_log_lock();
qemu_log("--------------\n");
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, last_pc + 4 - pc_start);
+ qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
+ log_target_disas(cs, dc->base.pc_first,
+ dc->base.pc_next - dc->base.pc_first);
qemu_log("\n");
qemu_log_unlock();
}
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH 3/3] target/sparc: convert to TranslatorOps
2018-02-15 23:17 [Qemu-devel] [PATCH 0/3] target/sparc: translator loop conversion Emilio G. Cota
2018-02-15 23:17 ` [Qemu-devel] [PATCH 1/3] target/sparc: convert to DisasJumpType Emilio G. Cota
2018-02-15 23:17 ` [Qemu-devel] [PATCH 2/3] target/sparc: convert to DisasContextBase Emilio G. Cota
@ 2018-02-15 23:17 ` Emilio G. Cota
2018-02-18 19:29 ` Richard Henderson
2 siblings, 1 reply; 7+ messages in thread
From: Emilio G. Cota @ 2018-02-15 23:17 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson, Mark Cave-Ayland, Artyom Tarasenko
Notes:
- Moved the cross-page check from the end of translate_insn to
init_disas_context.
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/sparc/translate.c | 181 +++++++++++++++++++++++------------------------
1 file changed, 88 insertions(+), 93 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index da77a27..5a25a51 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5732,105 +5732,94 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
}
-void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
+static int sparc_tr_init_disas_context(DisasContextBase *dcbase,
+ CPUState *cs, int max_insns)
{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUSPARCState *env = cs->env_ptr;
- DisasContext dc1, *dc = &dc1;
- int max_insns;
- unsigned int insn;
-
- memset(dc, 0, sizeof(DisasContext));
- dc->base.tb = tb;
- dc->base.pc_first = tb->pc;
- dc->base.pc_next = tb->pc;
- dc->base.is_jmp = DISAS_NEXT;
- dc->base.num_insns = 0;
- dc->base.singlestep_enabled = cs->singlestep_enabled;
+ int bound;
dc->pc = dc->base.pc_first;
- dc->npc = (target_ulong) tb->cs_base;
+ dc->npc = (target_ulong)dc->base.tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
- dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
+ dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
dc->def = &env->def;
- dc->fpu_enabled = tb_fpu_enabled(tb->flags);
- dc->address_mask_32bit = tb_am_enabled(tb->flags);
+ dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
+ dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
#ifndef CONFIG_USER_ONLY
- dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
+ dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
#endif
#ifdef TARGET_SPARC64
dc->fprs_dirty = 0;
- dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
+ dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
#ifndef CONFIG_USER_ONLY
- dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
+ dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
#endif
#endif
+ /*
+ * if we reach a page boundary, we stop generation so that the
+ * PC of a TT_TFAULT exception is always in the right page
+ */
+ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
+ return MIN(max_insns, bound);
+}
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
- if (singlestep) {
- max_insns = 1;
- }
+static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
+{
+}
- gen_tb_start(tb);
- do {
- if (dc->npc & JUMP_PC) {
- assert(dc->jump_pc[1] == dc->pc + 4);
- tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
- } else {
- tcg_gen_insn_start(dc->pc, dc->npc);
- }
- dc->base.num_insns++;
+static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
- if (dc->pc != dc->base.pc_first) {
- save_state(dc);
- }
- gen_helper_debug(cpu_env);
- tcg_gen_exit_tb(0);
- dc->base.is_jmp = DISAS_NORETURN;
- dc->base.pc_next += 4;
- goto exit_gen_loop;
- }
+ if (dc->npc & JUMP_PC) {
+ assert(dc->jump_pc[1] == dc->pc + 4);
+ tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
+ } else {
+ tcg_gen_insn_start(dc->pc, dc->npc);
+ }
+}
- if (dc->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
- insn = cpu_ldl_code(env, dc->pc);
- dc->base.pc_next += 4;
+ if (dc->pc != dc->base.pc_first) {
+ save_state(dc);
+ }
+ gen_helper_debug(cpu_env);
+ tcg_gen_exit_tb(0);
+ dc->base.is_jmp = DISAS_NORETURN;
+ /* update pc_next so that the current instruction is included in tb->size */
+ dc->base.pc_next += 4;
+ return true;
+}
- disas_sparc_insn(dc, insn);
+static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ CPUSPARCState *env = cs->env_ptr;
+ unsigned int insn;
- if (dc->base.is_jmp == DISAS_NORETURN) {
- break;
- }
- /* if the next PC is different, we abort now */
- if (dc->pc != dc->base.pc_next) {
- break;
- }
- /* if we reach a page boundary, we stop generation so that the
- PC of a TT_TFAULT exception is always in the right page */
- if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
- break;
- /* if single step mode, we generate only one instruction and
- generate an exception */
- if (dc->base.singlestep_enabled) {
- break;
- }
- } while (!tcg_op_buf_full() &&
- (dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) &&
- dc->base.num_insns < max_insns);
+ insn = cpu_ldl_code(env, dc->pc);
+ dc->base.pc_next += 4;
+ disas_sparc_insn(dc, insn);
- exit_gen_loop:
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
+ if (dc->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+ if (dc->pc != dc->base.pc_next ||
+ (dc->pc - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) {
+ dc->base.is_jmp = DISAS_TOO_MANY;
}
+}
+
+static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
if (dc->base.is_jmp != DISAS_NORETURN) {
if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
@@ -5844,23 +5833,29 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
tcg_gen_exit_tb(0);
}
}
- gen_tb_end(tb, dc->base.num_insns);
-
- tb->size = dc->base.pc_next - dc->base.pc_first;
- tb->icount = dc->base.num_insns;
-
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(dc->base.pc_first)) {
- qemu_log_lock();
- qemu_log("--------------\n");
- qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
- log_target_disas(cs, dc->base.pc_first,
- dc->base.pc_next - dc->base.pc_first);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
+}
+
+static void sparc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
+{
+ qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+ log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
+}
+
+static const TranslatorOps sparc_tr_ops = {
+ .init_disas_context = sparc_tr_init_disas_context,
+ .tb_start = sparc_tr_tb_start,
+ .insn_start = sparc_tr_insn_start,
+ .breakpoint_check = sparc_tr_breakpoint_check,
+ .translate_insn = sparc_tr_translate_insn,
+ .tb_stop = sparc_tr_tb_stop,
+ .disas_log = sparc_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+{
+ DisasContext dc = {};
+
+ translator_loop(&sparc_tr_ops, &dc.base, cs, tb);
}
void sparc_tcg_init(void)
--
2.7.4
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