From: weiwei <liweiwei@iscas.ac.cn>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: liweiwei@iscas.ac.cn, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate()
Date: Wed, 15 Feb 2023 10:57:34 +0800 [thread overview]
Message-ID: <5612a275-4902-a7e8-2f10-1f1fbd999adf@iscas.ac.cn> (raw)
In-Reply-To: <CAEUhbmX6Qb1aAdZC+d2F=n5qLo60XGiE3e0xTco1TgNgDxAKVg@mail.gmail.com>
On 2023/2/15 10:22, Bin Meng wrote:
> On Tue, Feb 14, 2023 at 10:59 PM weiwei <liweiwei@iscas.ac.cn> wrote:
>>
>> On 2023/2/14 22:27, Bin Meng wrote:
>>> At present the envcfg CSRs predicate() routines are generic one like
>>> smode(), hmode. The configuration check is done in the read / write
>>> routine. Create a new predicate routine to cover such check, so that
>>> gdbstub can correctly report its existence.
>>>
>>> Signed-off-by: Bin Meng <bmeng@tinylab.org>
>>>
>>> ---
>>>
>>> target/riscv/csr.c | 98 +++++++++++++++++++++++++++++-----------------
>>> 1 file changed, 61 insertions(+), 37 deletions(-)
>>>
>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>>> index 37350b8a6d..284ccc09dd 100644
>>> --- a/target/riscv/csr.c
>>> +++ b/target/riscv/csr.c
>>> @@ -41,40 +41,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
>>> }
>>>
>>> /* Predicates */
>>> -#if !defined(CONFIG_USER_ONLY)
>>> -static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
>>> - uint64_t bit)
>>> -{
>>> - bool virt = riscv_cpu_virt_enabled(env);
>>> - RISCVCPU *cpu = env_archcpu(env);
>>> -
>>> - if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
>>> - return RISCV_EXCP_NONE;
>>> - }
>>> -
>>> - if (!(env->mstateen[index] & bit)) {
>>> - return RISCV_EXCP_ILLEGAL_INST;
>>> - }
>>> -
>>> - if (virt) {
>>> - if (!(env->hstateen[index] & bit)) {
>>> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>>> - }
>>> -
>>> - if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
>>> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>>> - }
>>> - }
>>> -
>>> - if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
>>> - if (!(env->sstateen[index] & bit)) {
>>> - return RISCV_EXCP_ILLEGAL_INST;
>>> - }
>>> - }
>>> -
>>> - return RISCV_EXCP_NONE;
>>> -}
>>> -#endif
>>>
>>> static RISCVException fs(CPURISCVState *env, int csrno)
>>> {
>>> @@ -318,6 +284,32 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
>>> return umode(env, csrno);
>>> }
>>>
>>> +static RISCVException envcfg(CPURISCVState *env, int csrno)
>>> +{
>>> + RISCVCPU *cpu = env_archcpu(env);
>>> + riscv_csr_predicate_fn predicate;
>>> +
>>> + if (cpu->cfg.ext_smstateen) {
>>> + return RISCV_EXCP_ILLEGAL_INST;
>>> + }
>> This check seems not right here. Why ILLEGAL_INST is directly
>> triggered if smstateen is enabled?
> This logic was there in the original codes. I was confused when I
> looked at this as well.
Sorry, I didn't find the original codes. Do you mean this:
if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
return RISCV_EXCP_NONE;
}
If so, I think the check here is to make the following *stateen related
check ignored when smstateen extension is disabled.
Regards,
Weiwei Li
> Anyway, if it is an issue, it should be a separate patch.
>
>> It seems that smstateen related check will be done for
>> senvcfg/henvcfg{h} when smstateen is enabled.
>>
> Regards,
> Bin
next prev parent reply other threads:[~2023-02-15 2:58 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 18:01 [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-13 18:01 ` [PATCH 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-14 8:40 ` weiwei
2023-02-17 2:11 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 02/18] target/riscv: Correct the priority policy of riscv_csrrw_check() Bin Meng
2023-02-14 8:43 ` weiwei
2023-02-17 2:15 ` LIU Zhiwei
2023-02-13 18:01 ` [PATCH 03/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
2023-02-14 8:45 ` weiwei
2023-02-17 2:20 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 04/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
2023-02-14 8:46 ` weiwei
2023-02-17 2:23 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 05/18] target/riscv: Coding style fixes in csr.c Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 06/18] target/riscv: Use 'bool' type for read_only Bin Meng
2023-02-14 8:48 ` weiwei
2023-02-17 2:24 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 07/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
2023-02-14 8:50 ` [PATCH 07/18] target/riscv: Simplify {read,write}_pmpcfg() " weiwei
2023-02-17 2:26 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 08/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
2023-02-14 8:51 ` weiwei
2023-02-17 2:30 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
2023-02-14 8:56 ` weiwei
2023-02-17 2:36 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 10/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
2023-02-14 9:02 ` weiwei
2023-02-17 2:39 ` LIU Zhiwei
2023-02-13 18:02 ` [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
2023-02-14 9:13 ` weiwei
2023-02-17 2:43 ` LIU Zhiwei
2023-02-13 19:19 ` [PATCH 00/18] target/riscv: Various fixes to gdbstub and CSR access Daniel Henrique Barboza
2023-02-14 14:31 ` Bin Meng
2023-02-14 1:09 ` [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
2023-02-14 9:16 ` weiwei
2023-02-17 2:48 ` LIU Zhiwei
2023-02-14 1:09 ` [PATCH 13/18] target/riscv: Allow debugger to access seed CSR Bin Meng
2023-02-14 9:18 ` weiwei
2023-02-17 2:59 ` LIU Zhiwei
2023-02-14 3:06 ` [PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
2023-02-14 9:24 ` weiwei
2023-02-14 4:12 ` [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
2023-02-14 9:26 ` weiwei
2023-02-14 4:12 ` [PATCH 16/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-02-14 9:26 ` weiwei
2023-02-14 4:31 ` [PATCH 17/18] target/riscv: Group all predicate() routines together Bin Meng
2023-02-14 9:27 ` weiwei
2023-02-14 14:27 ` [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate() Bin Meng
2023-02-14 14:59 ` weiwei
2023-02-15 2:22 ` Bin Meng
2023-02-15 2:57 ` weiwei [this message]
2023-02-16 16:40 ` Palmer Dabbelt
2023-02-17 1:59 ` Bin Meng
2023-02-17 17:28 ` Palmer Dabbelt
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