[Qemu-devel] [PATCH] target-mips: Add SIGRIE instruction

[Qemu-devel] [PATCH] target-mips: Add SIGRIE instruction

[Yongbok Kim]

Add SIGRIE (Signal Reserved Instruction Exception).
The instruction allows to use the 16-bit code field for software use.
This instruction is introduced by and required as of Release 6.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
 target-mips/translate.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 4a47c2d..0af807a 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -323,6 +323,7 @@ enum {
     OPC_TLTIU    = (0x0B << 16) | OPC_REGIMM,
     OPC_TEQI     = (0x0C << 16) | OPC_REGIMM,
     OPC_TNEI     = (0x0E << 16) | OPC_REGIMM,
+    OPC_SIGRIE   = (0x17 << 16) | OPC_REGIMM,
     OPC_SYNCI    = (0x1F << 16) | OPC_REGIMM,
 
     OPC_DAHI     = (0x06 << 16) | OPC_REGIMM,
@@ -12017,7 +12018,8 @@ enum {
     LSA = 0x0f,
     ALIGN = 0x1f,
     EXT = 0x2c,
-    POOL32AXF = 0x3c
+    POOL32AXF = 0x3c,
+    SIGRIE = 0x3f
 };
 
 /* POOL32AXF encoding of minor opcode field extension */
@@ -13636,6 +13638,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
         case BREAK32:
             generate_exception_end(ctx, EXCP_BREAK);
             break;
+        case SIGRIE:
+            check_insn(ctx, ISA_MIPS32R6);
+            generate_exception_err(ctx, EXCP_RI, extract32(ctx->opcode, 6, 16));
+            break;
         default:
         pool32a_invalid:
                 MIPS_INVAL("pool32a");
@@ -18958,6 +18964,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
             check_insn_opc_removed(ctx, ISA_MIPS32R6);
             gen_trap(ctx, op1, rs, -1, imm);
             break;
+        case OPC_SIGRIE:
+            check_insn(ctx, ISA_MIPS32R6);
+            generate_exception_err(ctx, EXCP_RI, extract32(ctx->opcode, 0, 16));
+            break;
         case OPC_SYNCI:
             check_insn(ctx, ISA_MIPS32R2);
             /* Break the TB to be able to sync copied instructions
-- 
1.7.1

Re: [Qemu-devel] [PATCH] target-mips: Add SIGRIE instruction

[Leon Alrae]

On 05/10/15 10:33, Yongbok Kim wrote:
> @@ -18958,6 +18964,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
>              check_insn_opc_removed(ctx, ISA_MIPS32R6);
>              gen_trap(ctx, op1, rs, -1, imm);
>              break;
> +        case OPC_SIGRIE:
> +            check_insn(ctx, ISA_MIPS32R6);
> +            generate_exception_err(ctx, EXCP_RI, extract32(ctx->opcode, 0, 16));

Code field is passed as the error_code, but it isn't used later anywhere
and just causes confusion. MIPS BIS document doesn't require any
specific behaviour related to this field, thus in QEMU we should ignore
it and just call generate_exception_end(ctx, EXCP_RI) here.

Leon