From: Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
To: David Kiarie <davidkiarie4@gmail.com>,
qemu-devel@nongnu.org, jan.kiszka@web.de, mst@redhat.com
Subject: Re: [Qemu-devel] [PATCH 0/4] AMD IOMMU v1
Date: Fri, 9 Oct 2015 12:17:07 +0500 [thread overview]
Message-ID: <561769F3.4000506@gmail.com> (raw)
In-Reply-To: <1444359237-27224-1-git-send-email-davidkiarie4@gmail.com>
Hi David,
Thanks for your efforts.
On 09.10.2015 07:53, David Kiarie wrote:
> David (4):
> hw/core: Add iommu to machine properties
> hw/pci-host: Add AMD IOMMU to PIIX and Q35 pcs
> hw/i386: Introduce AMD IOMMU
> hw/acpi: ACPI table for AMD IOMMU
>
> hw/core/machine.c | 25 +
> hw/i386/Makefile.objs | 1 +
> hw/i386/acpi-build.c | 85 +++
> hw/i386/amd_iommu.c | 1266 +++++++++++++++++++++++++++++++++++++++++++
> hw/i386/amd_iommu.h | 363 +++++++++++++
> hw/pci-host/piix.c | 10 +
> hw/pci-host/q35.c | 10 +
> include/hw/acpi/acpi-defs.h | 55 ++
> include/hw/boards.h | 2 +
> 9 files changed, 1817 insertions(+)
> create mode 100644 hw/i386/amd_iommu.c
> create mode 100644 hw/i386/amd_iommu.h
>
>
> AMD IOMMU v1
>
> Changes since RFC
> -code cleanup around MMIO code
> -compacted startup code - some of the 'init' and 'reset' code is similar and can be reused
> -Implemented basic IOTLB - it's just a hashtable of already requested virtual address translations whereby if a device requests translation of the same address we don't have to do a page walk, again.
> -Implemented event logging - this version logs about all possible SW/HW errors but most of them are very unlikely to occur.
> -Changed GVA and HVA to go by the physical host bus implementations - 48 bits virtual and 40 bits physical address space.
I haven't looked into this closely yet, but shouldn't you support a
whole 63 bits wide addresses (and 6-level page tables), as per
specification?
>
> TODO
> -Implement MMIO reserving code
> -Implement r/wc MMIO registers
> -Implement interrupts related to r/wc registers
>
> IOMMU won't be able to implement PPR logging with the current Qemu infrastructure - Qemu doesn't implement anything that's related to PASID. Similary, guest translation won't be possible.
>
> Note: I have not tested this code and it might have a few bugs (silly bugs) of course but the RFC version works so, if present, it's just minor bugs.
Regards,
Valentine Sinitsyn
next prev parent reply other threads:[~2015-10-09 7:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-09 2:53 [Qemu-devel] [PATCH 0/4] AMD IOMMU v1 David Kiarie
2015-10-09 2:53 ` [Qemu-devel] [PATCH 1/4] hw/core: Add iommu to machine properties David Kiarie
2015-10-08 18:10 ` Marcel Apfelbaum
2015-10-09 12:17 ` David kiarie
2015-10-09 17:16 ` Peter Crosthwaite
2015-10-09 2:53 ` [Qemu-devel] [PATCH 2/4] hw/pci-host: Add AMD IOMMU to PIIX and Q35 pcs David Kiarie
2015-10-08 12:11 ` Michael S. Tsirkin
2015-10-08 14:40 ` Marcel Apfelbaum
2015-10-09 2:53 ` [Qemu-devel] [PATCH 3/4] hw/i386: Introduce AMD IOMMU David Kiarie
2015-10-08 18:24 ` Marcel Apfelbaum
2015-10-09 12:20 ` David kiarie
2015-10-09 2:53 ` [Qemu-devel] [PATCH 4/4] hw/acpi: ACPI table for " David Kiarie
2015-10-09 7:17 ` Valentine Sinitsyn [this message]
2015-10-09 12:22 ` [Qemu-devel] [PATCH 0/4] AMD IOMMU v1 David kiarie
2015-10-09 12:24 ` Valentine Sinitsyn
2015-10-09 12:27 ` David kiarie
2015-10-09 12:30 ` Valentine Sinitsyn
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