From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49510) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkWoV-0000ev-OB for qemu-devel@nongnu.org; Fri, 09 Oct 2015 08:30:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZkWoU-0002Jo-Ko for qemu-devel@nongnu.org; Fri, 09 Oct 2015 08:30:19 -0400 Received: from mail-lb0-x231.google.com ([2a00:1450:4010:c04::231]:35328) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkWoU-0002JD-8y for qemu-devel@nongnu.org; Fri, 09 Oct 2015 08:30:18 -0400 Received: by lbwr8 with SMTP id r8so78452685lbw.2 for ; Fri, 09 Oct 2015 05:30:17 -0700 (PDT) References: <1444359237-27224-1-git-send-email-davidkiarie4@gmail.com> <561769F3.4000506@gmail.com> <5617B219.5040305@gmail.com> From: Valentine Sinitsyn Message-ID: <5617B356.4080207@gmail.com> Date: Fri, 9 Oct 2015 17:30:14 +0500 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 0/4] AMD IOMMU v1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David kiarie Cc: Jan Kiszka , QEMU Developers , mst@redhat.com On 09.10.2015 17:27, David kiarie wrote: > On Fri, Oct 9, 2015 at 3:24 PM, Valentine Sinitsyn > wrote: >> On 09.10.2015 17:22, David kiarie wrote: >>> >>> On Fri, Oct 9, 2015 at 10:17 AM, Valentine Sinitsyn >>> wrote: >>>> >>>> Hi David, >>>> >>>> Thanks for your efforts. >>>> >>>> >>>> On 09.10.2015 07:53, David Kiarie wrote: >>>>> >>>>> >>>>> David (4): >>>>> hw/core: Add iommu to machine properties >>>>> hw/pci-host: Add AMD IOMMU to PIIX and Q35 pcs >>>>> hw/i386: Introduce AMD IOMMU >>>>> hw/acpi: ACPI table for AMD IOMMU >>>>> >>>>> hw/core/machine.c | 25 + >>>>> hw/i386/Makefile.objs | 1 + >>>>> hw/i386/acpi-build.c | 85 +++ >>>>> hw/i386/amd_iommu.c | 1266 >>>>> +++++++++++++++++++++++++++++++++++++++++++ >>>>> hw/i386/amd_iommu.h | 363 +++++++++++++ >>>>> hw/pci-host/piix.c | 10 + >>>>> hw/pci-host/q35.c | 10 + >>>>> include/hw/acpi/acpi-defs.h | 55 ++ >>>>> include/hw/boards.h | 2 + >>>>> 9 files changed, 1817 insertions(+) >>>>> create mode 100644 hw/i386/amd_iommu.c >>>>> create mode 100644 hw/i386/amd_iommu.h >>>>> >>>>> >>>>> AMD IOMMU v1 >>>>> >>>>> Changes since RFC >>>>> -code cleanup around MMIO code >>>>> -compacted startup code - some of the 'init' and 'reset' code is >>>>> similar and can be reused >>>>> -Implemented basic IOTLB - it's just a hashtable of already >>>>> requested >>>>> virtual address translations whereby if a device requests translation of >>>>> the >>>>> same address we don't have to do a page walk, again. >>>>> -Implemented event logging - this version logs about all possible >>>>> SW/HW errors but most of them are very unlikely to occur. >>>>> -Changed GVA and HVA to go by the physical host bus >>>>> implementations - >>>>> 48 bits virtual and 40 bits physical address space. >>>> >>>> >>>> I haven't looked into this closely yet, but shouldn't you support a whole >>>> 63 >>>> bits wide addresses (and 6-level page tables), as per specification? >>>> >>> Am not sure too. >>> >>> When I tested this, linux was using 3-level pages. >> >> Nobody uses whole 6 page table levels, to the best of my knowledge. >> Supporting (emulating) them, however, is part of the spec. Besides, it will >> be needed if one decides to share page tables between IOMMU and CPU >> > > Should I use 6 levels/64 bit virtual address space ? I think so, but let me look through the patch series first. That was a quick question - I just got surprised that you made it narrower than it was. Valentine > >>> >>> I went with 48 bits as AFAIK that's what current hardware works. This >>> code should work with 6-levels though I just used 48 to be 'safe'. >>> >>>>> >>>>> TODO >>>>> -Implement MMIO reserving code >>>>> -Implement r/wc MMIO registers >>>>> -Implement interrupts related to r/wc registers >>>>> >>>>> IOMMU won't be able to implement PPR logging with the current Qemu >>>>> infrastructure - Qemu doesn't implement anything that's related to >>>>> PASID. >>>>> Similary, guest translation won't be possible. >>>>> >>>>> Note: I have not tested this code and it might have a few bugs (silly >>>>> bugs) of course but the RFC version works so, if present, it's just >>>>> minor >>>>> bugs. >>>> >>>> >>>> >>>> Regards, >>>> Valentine Sinitsyn >> >> >> Regards, >> Valentine Sinitsyn