From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:48361)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <mdavidsaver@gmail.com>) id 1ZlU8f-0006eq-Sy
	for qemu-devel@nongnu.org; Sun, 11 Oct 2015 23:51:06 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <mdavidsaver@gmail.com>) id 1ZlU8b-0002JW-Sk
	for qemu-devel@nongnu.org; Sun, 11 Oct 2015 23:51:05 -0400
Received: from mail-qg0-x22f.google.com ([2607:f8b0:400d:c04::22f]:33676)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <mdavidsaver@gmail.com>) id 1ZlU8b-0002JC-P1
	for qemu-devel@nongnu.org; Sun, 11 Oct 2015 23:51:01 -0400
Received: by qgeb31 with SMTP id b31so10638040qge.0
	for <qemu-devel@nongnu.org>; Sun, 11 Oct 2015 20:51:01 -0700 (PDT)
Message-ID: <561B2E24.9020600@gmail.com>
Date: Sun, 11 Oct 2015 23:51:00 -0400
From: Michael Davidsaver <mdavidsaver@gmail.com>
MIME-Version: 1.0
References: <cover.1444396783.git.mdavidsaver@gmail.com>	<c0d3b1169ee079ef9a2bd00d62d6720c8367ae41.1444396783.git.mdavidsaver@gmail.com>
	<CAPokK=qdfBqCR5nfK4toekX7AVzRHkOLr=4pi5imgavWKN_kRg@mail.gmail.com>
In-Reply-To: <CAPokK=qdfBqCR5nfK4toekX7AVzRHkOLr=4pi5imgavWKN_kRg@mail.gmail.com>
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH 3/3] armv7-m: add MPU to cortex-m3 and
	cortex-m4
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>

On 10/11/2015 11:23 AM, Peter Crosthwaite wrote:
> On Fri, Oct 9, 2015 at 6:28 AM, Michael Davidsaver
> <mdavidsaver@gmail.com> wrote:
>> The M series MPU is almost the same as the already
>> implemented R series MPU.  So use the M series
>> and translate as best we can.
>>
> There is some work on list for this that never got a respin:
>
> https://lists.gnu.org/archive/html/qemu-devel/2015-07/msg01945.html

Well, I totally missed that.  I'll have look.

> ...
>> +    case 0xd34: /* MMFAR MemManage Fault Address */
>> +        return ARM_CPU(current_cpu)->pmsav7_mmfar;
> Why reorder the addresses in the switch?

I was thinking to avoid duplicating the qemu_log_mask() for the
unimplemented registers.  I take it that this to you is not the lesser
evil :)

> ... If you run your patch through scripts/checkpatch.pl it will detect
> some of these conventions. 

Will do.

> ... More style nits here....

All noted.

> Regards, Peter 

Michael