From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34646) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZlcPs-00028U-1h for qemu-devel@nongnu.org; Mon, 12 Oct 2015 08:41:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZlcPg-0004fF-UY for qemu-devel@nongnu.org; Mon, 12 Oct 2015 08:41:17 -0400 Received: from mail-lb0-x236.google.com ([2a00:1450:4010:c04::236]:34363) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZlcPg-0004f3-Nc for qemu-devel@nongnu.org; Mon, 12 Oct 2015 08:41:12 -0400 Received: by lbbck17 with SMTP id ck17so21343077lbb.1 for ; Mon, 12 Oct 2015 05:41:11 -0700 (PDT) From: Sergey Fedorov References: <1443434870-5702-1-git-send-email-serge.fdrv@gmail.com> <1443434870-5702-3-git-send-email-serge.fdrv@gmail.com> Message-ID: <561BAA65.8030907@gmail.com> Date: Mon, 12 Oct 2015 15:41:09 +0300 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v2 2/2] target-arm: Fix CPU breakpoint handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers On 08.10.2015 21:40, Peter Maydell wrote: > Annoying corner case which I don't think we need to handle necessarily: > if you set a breakpoint on a 32-bit Thumb instruction which spans a page > boundary, and the second page is not present, we will end up taking the > page fault when I think we should take the breakpoint. I can't think > of a way to get that right, so just commenting that it isn't handled > right would do. What I found in ARM ARMv8 (DDI0487A_g) section G2.9.1 About Breakpoint exceptions: For each instruction in the program flow, all of the breakpoints are tested. When a breakpoint is tested, it generates a Breakpoint debug event if all of the following are true: • The breakpoint is enabled. That is, the breakpoint enable control for it, DBGBCR.E, is 1. • The conditions specified in the DBGBCR are met. • The comparisons with the values held in one or both of the DBGBVR and DBGBXVR, as applicable, are successful. • If the breakpoint is linked to another breakpoint, the comparisons made by that other breakpoint are also successful. • The instruction is committed for execution. If I understand correctly, the last item in the list specifies that any page fault exception which would occur in the normal instruction execution has more priority than the breakpoint exception. If so, Everything should be okay. Best regards, Sergey