From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zn4Ip-0004gV-Ne for qemu-devel@nongnu.org; Fri, 16 Oct 2015 08:40:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zn4Im-0005os-Fh for qemu-devel@nongnu.org; Fri, 16 Oct 2015 08:40:07 -0400 Received: from mail-lb0-x235.google.com ([2a00:1450:4010:c04::235]:35564) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zn4Im-0005oC-9b for qemu-devel@nongnu.org; Fri, 16 Oct 2015 08:40:04 -0400 Received: by lbbes7 with SMTP id es7so9786102lbb.2 for ; Fri, 16 Oct 2015 05:40:03 -0700 (PDT) References: <1444383794-16767-1-git-send-email-serge.fdrv@gmail.com> From: Sergey Fedorov Message-ID: <5620F021.3070800@gmail.com> Date: Fri, 16 Oct 2015 15:40:01 +0300 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] target-arm: Add MDCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers On 16.10.2015 15:34, Peter Maydell wrote: > On 9 October 2015 at 10:43, Sergey Fedorov wrote: >> Signed-off-by: Sergey Fedorov >> --- >> >> Changes in v2: >> * Reset value is simply made zero >> >> target-arm/cpu.h | 1 + >> target-arm/helper.c | 11 +++++++++++ >> 2 files changed, 12 insertions(+) >> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index cc1578c..51d8ed1 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -378,6 +378,7 @@ typedef struct CPUARMState { >> uint64_t dbgwvr[16]; /* watchpoint value registers */ >> uint64_t dbgwcr[16]; /* watchpoint control registers */ >> uint64_t mdscr_el1; >> + uint64_t mdcr_el2; >> /* If the counter is enabled, this stores the last time the counter >> * was reset. Otherwise it stores the counter value >> */ >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 8367997..ec4097b 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -3223,6 +3223,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, >> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, >> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >> + { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, >> + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, >> + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >> REGINFO_SENTINEL >> }; >> >> @@ -3576,6 +3579,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { >> { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64, >> .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0, >> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, >> + /* The only field of MDCR_EL2 that has a defined architectural reset value >> + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we >> + * don't impelment any PMU event counters, so using zero as a reset >> + * value for MDCR_EL2 is okay */ >> + { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, >> + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, >> + .access = PL2_RW, .resetvalue = 0, >> + .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }, >> { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, >> .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, >> /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */ > This fails 'make check': > > GTESTER check-qtest-arm > Register redefined: cp=15 32 bit crn=1 crm=1 opc1=4 opc2=1, was > MDCR_EL2, now MDCR_EL2 > ** > ERROR:/home/petmay01/linaro/qemu-from-laptop/qemu/target-arm/helper.c:4740:add_cpreg_to_hashtable: > code should not be reached > > The second MDCR_EL2 definition needs to be in el2_cp_reginfo[], > not debug_cp_reginfo[]; otherwise a CPU with EL2 but not EL2 > will try to define both. > > I will squash in the change which moves the definition. Oops... I should make it a rule and do 'make check' before submitting changes. Thanks, Sergey