* [Qemu-devel] [PATCH v2 1/9] target-i386: Introduce cpu_x86_update_dr7
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 2/9] target-i386: Re-introduce optimal breakpoint removal Eduardo Habkost
` (7 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
This moves the last of the iteration over breakpoints into
the bpt_helper.c file. This also allows us to make several
breakpoint functions static.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/bpt_helper.c | 29 ++++++++++++++++++-----------
target-i386/cpu.h | 4 ++--
target-i386/machine.c | 8 ++++++--
target-i386/seg_helper.c | 8 +-------
4 files changed, 27 insertions(+), 22 deletions(-)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index c071c24..f14788a 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -21,7 +21,8 @@
#include "exec/helper-proto.h"
-void hw_breakpoint_insert(CPUX86State *env, int index)
+#ifndef CONFIG_USER_ONLY
+static void hw_breakpoint_insert(CPUX86State *env, int index)
{
CPUState *cs = CPU(x86_env_get_cpu(env));
int type = 0, err = 0;
@@ -55,7 +56,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index)
}
}
-void hw_breakpoint_remove(CPUX86State *env, int index)
+static void hw_breakpoint_remove(CPUX86State *env, int index)
{
CPUState *cs;
@@ -79,6 +80,20 @@ void hw_breakpoint_remove(CPUX86State *env, int index)
}
}
+void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
+{
+ int i;
+
+ for (i = 0; i < DR7_MAX_BP; i++) {
+ hw_breakpoint_remove(env, i);
+ }
+ env->dr[7] = new_dr7;
+ for (i = 0; i < DR7_MAX_BP; i++) {
+ hw_breakpoint_insert(env, i);
+ }
+}
+#endif
+
static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
{
target_ulong dr6;
@@ -161,20 +176,12 @@ void helper_single_step(CPUX86State *env)
void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
#ifndef CONFIG_USER_ONLY
- int i;
-
if (reg < 4) {
hw_breakpoint_remove(env, reg);
env->dr[reg] = t0;
hw_breakpoint_insert(env, reg);
} else if (reg == 7) {
- for (i = 0; i < DR7_MAX_BP; i++) {
- hw_breakpoint_remove(env, i);
- }
- env->dr[7] = t0;
- for (i = 0; i < DR7_MAX_BP; i++) {
- hw_breakpoint_insert(env, i);
- }
+ cpu_x86_update_dr7(env, t0);
} else {
env->dr[reg] = t0;
}
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 54d9d50..c818801 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -235,6 +235,7 @@
#define DR7_TYPE_SHIFT 16
#define DR7_LEN_SHIFT 18
#define DR7_FIXED_1 0x00000400
+#define DR7_GLOBAL_BP_MASK 0xaa
#define DR7_LOCAL_BP_MASK 0x55
#define DR7_MAX_BP 4
#define DR7_TYPE_BP_INST 0x0
@@ -1153,14 +1154,13 @@ static inline int hw_breakpoint_len(unsigned long dr7, int index)
return (len == 2) ? 8 : len + 1;
}
-void hw_breakpoint_insert(CPUX86State *env, int index);
-void hw_breakpoint_remove(CPUX86State *env, int index);
void breakpoint_handler(CPUState *cs);
/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
+void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 9fa0563..f2d8d56 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -367,8 +367,12 @@ static int cpu_post_load(void *opaque, int version_id)
cpu_breakpoint_remove_all(cs, BP_CPU);
cpu_watchpoint_remove_all(cs, BP_CPU);
- for (i = 0; i < DR7_MAX_BP; i++) {
- hw_breakpoint_insert(env, i);
+ {
+ /* Indicate all breakpoints disabled, as they are, then
+ let the helper re-enable them. */
+ target_ulong dr7 = env->dr[7];
+ env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
+ cpu_x86_update_dr7(env, dr7);
}
tlb_flush(cs, 1);
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 1cbe559..20ee892 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -501,13 +501,7 @@ static void switch_tss_ra(CPUX86State *env, int tss_selector,
#ifndef CONFIG_USER_ONLY
/* reset local breakpoints */
if (env->dr[7] & DR7_LOCAL_BP_MASK) {
- for (i = 0; i < DR7_MAX_BP; i++) {
- if (hw_local_breakpoint_enabled(env->dr[7], i) &&
- !hw_global_breakpoint_enabled(env->dr[7], i)) {
- hw_breakpoint_remove(env, i);
- }
- }
- env->dr[7] &= ~DR7_LOCAL_BP_MASK;
+ cpu_x86_update_dr7(env, env->dr[7] & ~DR7_LOCAL_BP_MASK);
}
#endif
}
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH v2 2/9] target-i386: Re-introduce optimal breakpoint removal
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 1/9] target-i386: Introduce cpu_x86_update_dr7 Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 3/9] target-i386: Ensure bit 10 on DR7 is never cleared Eduardo Habkost
` (6 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Before the last patch, we had an efficient loop that disabled
local breakpoints on task switch. Re-add that, but in a more
general way that handles changes to the global enable bits too.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v1 -> v2:
* Included fix from Paolo to make sure dr7 is updated after
hw_breakpoint_remove() call and before hw_breakpoint_insert()
call
---
target-i386/bpt_helper.c | 34 ++++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index f14788a..23ce828 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -82,14 +82,36 @@ static void hw_breakpoint_remove(CPUX86State *env, int index)
void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
{
+ target_ulong old_dr7 = env->dr[7];
int i;
- for (i = 0; i < DR7_MAX_BP; i++) {
- hw_breakpoint_remove(env, i);
- }
- env->dr[7] = new_dr7;
- for (i = 0; i < DR7_MAX_BP; i++) {
- hw_breakpoint_insert(env, i);
+ /* If nothing is changing except the global/local enable bits,
+ then we can make the change more efficient. */
+ if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {
+ /* Fold the global and local enable bits together into the
+ global fields, then xor to show which registers have
+ changed collective enable state. */
+ int mod = ((old_dr7 | old_dr7 * 2) ^ (new_dr7 | new_dr7 * 2)) & 0xff;
+
+ for (i = 0; i < DR7_MAX_BP; i++) {
+ if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {
+ hw_breakpoint_remove(env, i);
+ }
+ }
+ env->dr[7] = new_dr7;
+ for (i = 0; i < DR7_MAX_BP; i++) {
+ if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
+ hw_breakpoint_insert(env, i);
+ }
+ }
+ } else {
+ for (i = 0; i < DR7_MAX_BP; i++) {
+ hw_breakpoint_remove(env, i);
+ }
+ env->dr[7] = new_dr7;
+ for (i = 0; i < DR7_MAX_BP; i++) {
+ hw_breakpoint_insert(env, i);
+ }
}
}
#endif
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH v2 3/9] target-i386: Ensure bit 10 on DR7 is never cleared
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 1/9] target-i386: Introduce cpu_x86_update_dr7 Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 2/9] target-i386: Re-introduce optimal breakpoint removal Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-18 22:58 ` Richard Henderson
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 4/9] target-i386: Move hw_*breakpoint_* functions Eduardo Habkost
` (5 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
Bit 10 of DR7 is documented as always set to 1, so ensure that's
always the case.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/bpt_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index 23ce828..493deba 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -113,6 +113,8 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
hw_breakpoint_insert(env, i);
}
}
+
+ env->dr[7] |= DR7_FIXED_1;
}
#endif
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/9] target-i386: Ensure bit 10 on DR7 is never cleared
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 3/9] target-i386: Ensure bit 10 on DR7 is never cleared Eduardo Habkost
@ 2015-10-18 22:58 ` Richard Henderson
0 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2015-10-18 22:58 UTC (permalink / raw)
To: Eduardo Habkost, qemu-devel, Paolo Bonzini
On 10/16/2015 06:23 AM, Eduardo Habkost wrote:
> Bit 10 of DR7 is documented as always set to 1, so ensure that's
> always the case.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> target-i386/bpt_helper.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
> index 23ce828..493deba 100644
> --- a/target-i386/bpt_helper.c
> +++ b/target-i386/bpt_helper.c
> @@ -113,6 +113,8 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
> hw_breakpoint_insert(env, i);
> }
> }
> +
> + env->dr[7] |= DR7_FIXED_1;
Better to do this to new_dr7, above the xor test with old_dr7, so that we still
pass the xor test.
r~
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 4/9] target-i386: Move hw_*breakpoint_* functions
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
` (2 preceding siblings ...)
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 3/9] target-i386: Ensure bit 10 on DR7 is never cleared Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 5/9] target-i386: Optimize setting dr[0-3] Eduardo Habkost
` (4 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
They're only used from bpt_helper.c now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/bpt_helper.c | 29 ++++++++++++++++++++++++++++-
target-i386/cpu.h | 27 ---------------------------
2 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index 493deba..afa28df 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -22,6 +22,33 @@
#ifndef CONFIG_USER_ONLY
+static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
+{
+ return (dr7 >> (index * 2)) & 1;
+}
+
+static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
+{
+ return (dr7 >> (index * 2)) & 2;
+
+}
+static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
+{
+ return hw_global_breakpoint_enabled(dr7, index) ||
+ hw_local_breakpoint_enabled(dr7, index);
+}
+
+static inline int hw_breakpoint_type(unsigned long dr7, int index)
+{
+ return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
+}
+
+static inline int hw_breakpoint_len(unsigned long dr7, int index)
+{
+ int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
+ return (len == 2) ? 8 : len + 1;
+}
+
static void hw_breakpoint_insert(CPUX86State *env, int index)
{
CPUState *cs = CPU(x86_env_get_cpu(env));
@@ -116,7 +143,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
env->dr[7] |= DR7_FIXED_1;
}
-#endif
static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
{
@@ -187,6 +213,7 @@ void breakpoint_handler(CPUState *cs)
}
}
}
+#endif
void helper_single_step(CPUX86State *env)
{
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c818801..c9e4edf 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1127,33 +1127,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
#endif
-static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
-{
- return (dr7 >> (index * 2)) & 1;
-}
-
-static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
-{
- return (dr7 >> (index * 2)) & 2;
-
-}
-static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
-{
- return hw_global_breakpoint_enabled(dr7, index) ||
- hw_local_breakpoint_enabled(dr7, index);
-}
-
-static inline int hw_breakpoint_type(unsigned long dr7, int index)
-{
- return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
-}
-
-static inline int hw_breakpoint_len(unsigned long dr7, int index)
-{
- int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
- return (len == 2) ? 8 : len + 1;
-}
-
void breakpoint_handler(CPUState *cs);
/* will be suppressed */
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH v2 5/9] target-i386: Optimize setting dr[0-3]
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
` (3 preceding siblings ...)
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 4/9] target-i386: Move hw_*breakpoint_* functions Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints Eduardo Habkost
` (3 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
If the debug register is not enabled, we need
do nothing besides update the register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/bpt_helper.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index afa28df..0563abd 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -228,9 +228,14 @@ void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
{
#ifndef CONFIG_USER_ONLY
if (reg < 4) {
- hw_breakpoint_remove(env, reg);
- env->dr[reg] = t0;
- hw_breakpoint_insert(env, reg);
+ if (hw_breakpoint_enabled(env->dr[7], reg)
+ && hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
+ hw_breakpoint_remove(env, reg);
+ env->dr[reg] = t0;
+ hw_breakpoint_insert(env, reg);
+ } else {
+ env->dr[reg] = t0;
+ }
} else if (reg == 7) {
cpu_x86_update_dr7(env, t0);
} else {
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
` (4 preceding siblings ...)
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 5/9] target-i386: Optimize setting dr[0-3] Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-19 17:30 ` Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 7/9] target-i386: Check CR4[DE] for processing DR4/DR5 Eduardo Habkost
` (2 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v1 -> v2:
* Rebase on top of new version of "Re-introduce optimal breakpoint
removal"
---
target-i386/bpt_helper.c | 98 +++++++++++++++++++++++++++++++++++-------------
target-i386/cpu.h | 2 +
target-i386/helper.h | 1 +
target-i386/translate.c | 20 +++++++++-
4 files changed, 93 insertions(+), 28 deletions(-)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index 0563abd..00f3942 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -49,60 +49,72 @@ static inline int hw_breakpoint_len(unsigned long dr7, int index)
return (len == 2) ? 8 : len + 1;
}
-static void hw_breakpoint_insert(CPUX86State *env, int index)
+static int hw_breakpoint_insert(CPUX86State *env, int index)
{
CPUState *cs = CPU(x86_env_get_cpu(env));
- int type = 0, err = 0;
+ target_ulong dr7 = env->dr[7];
+ target_ulong drN = env->dr[index];
+ int err = 0;
- switch (hw_breakpoint_type(env->dr[7], index)) {
+ switch (hw_breakpoint_type(dr7, index)) {
case DR7_TYPE_BP_INST:
- if (hw_breakpoint_enabled(env->dr[7], index)) {
- err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,
+ if (hw_breakpoint_enabled(dr7, index)) {
+ err = cpu_breakpoint_insert(cs, drN, BP_CPU,
&env->cpu_breakpoint[index]);
}
break;
- case DR7_TYPE_DATA_WR:
- type = BP_CPU | BP_MEM_WRITE;
- break;
+
case DR7_TYPE_IO_RW:
- /* No support for I/O watchpoints yet */
+ /* Notice when we should enable calls to bpt_io. */
+ return (hw_breakpoint_enabled(env->dr[7], index)
+ ? HF_IOBPT_MASK : 0);
+
+ case DR7_TYPE_DATA_WR:
+ if (hw_breakpoint_enabled(dr7, index)) {
+ err = cpu_watchpoint_insert(cs, drN,
+ hw_breakpoint_len(dr7, index),
+ BP_CPU | BP_MEM_WRITE,
+ &env->cpu_watchpoint[index]);
+ }
break;
+
case DR7_TYPE_DATA_RW:
- type = BP_CPU | BP_MEM_ACCESS;
+ if (hw_breakpoint_enabled(dr7, index)) {
+ err = cpu_watchpoint_insert(cs, drN,
+ hw_breakpoint_len(dr7, index),
+ BP_CPU | BP_MEM_ACCESS,
+ &env->cpu_watchpoint[index]);
+ }
break;
}
-
- if (type != 0) {
- err = cpu_watchpoint_insert(cs, env->dr[index],
- hw_breakpoint_len(env->dr[7], index),
- type, &env->cpu_watchpoint[index]);
- }
-
if (err) {
env->cpu_breakpoint[index] = NULL;
}
+ return 0;
}
static void hw_breakpoint_remove(CPUX86State *env, int index)
{
- CPUState *cs;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
- if (!env->cpu_breakpoint[index]) {
- return;
- }
- cs = CPU(x86_env_get_cpu(env));
switch (hw_breakpoint_type(env->dr[7], index)) {
case DR7_TYPE_BP_INST:
- if (hw_breakpoint_enabled(env->dr[7], index)) {
+ if (env->cpu_breakpoint[index]) {
cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
+ env->cpu_breakpoint[index] = NULL;
}
break;
+
case DR7_TYPE_DATA_WR:
case DR7_TYPE_DATA_RW:
- cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
+ if (env->cpu_breakpoint[index]) {
+ cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
+ env->cpu_breakpoint[index] = NULL;
+ }
break;
+
case DR7_TYPE_IO_RW:
- /* No support for I/O watchpoints yet */
+ /* HF_IOBPT_MASK cleared elsewhere. */
break;
}
}
@@ -110,6 +122,7 @@ static void hw_breakpoint_remove(CPUX86State *env, int index)
void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
{
target_ulong old_dr7 = env->dr[7];
+ int iobpt = 0;
int i;
/* If nothing is changing except the global/local enable bits,
@@ -128,7 +141,10 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
env->dr[7] = new_dr7;
for (i = 0; i < DR7_MAX_BP; i++) {
if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
- hw_breakpoint_insert(env, i);
+ iobpt |= hw_breakpoint_insert(env, i);
+ } else if (hw_breakpoint_type(new_dr7, i) == DR7_TYPE_IO_RW
+ && hw_breakpoint_enabled(new_dr7, i)) {
+ iobpt |= HF_IOBPT_MASK;
}
}
} else {
@@ -137,11 +153,12 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
}
env->dr[7] = new_dr7;
for (i = 0; i < DR7_MAX_BP; i++) {
- hw_breakpoint_insert(env, i);
+ iobpt |= hw_breakpoint_insert(env, i);
}
}
env->dr[7] |= DR7_FIXED_1;
+ env->hflags = (env->hflags & ~HF_IOBPT_MASK) | iobpt;
}
static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
@@ -243,3 +260,30 @@ void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
}
#endif
}
+
+/* Check if Port I/O is trapped by a breakpoint. */
+void helper_bpt_io(CPUX86State *env, uint32_t port,
+ uint32_t size, target_ulong next_eip)
+{
+#ifndef CONFIG_USER_ONLY
+ target_ulong dr7 = env->dr[7];
+ int i, hit = 0;
+
+ for (i = 0; i < DR7_MAX_BP; ++i) {
+ if (hw_breakpoint_type(dr7, i) == DR7_TYPE_IO_RW
+ && hw_breakpoint_enabled(dr7, i)) {
+ int bpt_len = hw_breakpoint_len(dr7, i);
+ if (port + size - 1 >= env->dr[i]
+ && port <= env->dr[i] + bpt_len - 1) {
+ hit |= 1 << i;
+ }
+ }
+ }
+
+ if (hit) {
+ env->dr[6] = (env->dr[6] & ~0xf) | hit;
+ env->eip = next_eip;
+ raise_exception(env, EXCP01_DB);
+ }
+#endif
+}
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c9e4edf..649d54a 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -155,6 +155,7 @@
#define HF_SVMI_SHIFT 21 /* SVM intercepts are active */
#define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
#define HF_SMAP_SHIFT 23 /* CR4.SMAP */
+#define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
@@ -178,6 +179,7 @@
#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
+#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
/* hflags2 */
diff --git a/target-i386/helper.h b/target-i386/helper.h
index 8454a04..e9858c0 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -92,6 +92,7 @@ DEF_HELPER_3(outw, void, env, i32, i32)
DEF_HELPER_2(inw, tl, env, i32)
DEF_HELPER_3(outl, void, env, i32, i32)
DEF_HELPER_2(inl, tl, env, i32)
+DEF_HELPER_FLAGS_4(bpt_io, TCG_CALL_NO_WG, void, env, i32, i32, tl)
DEF_HELPER_3(svm_check_intercept_param, void, env, i32, i64)
DEF_HELPER_3(vmexit, void, env, i32, i64)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ef10e68..ceed4d1 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1154,6 +1154,19 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
gen_op_add_reg_T0(s->aflag, R_EDI);
}
+static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)
+{
+ if (s->flags & HF_IOBPT_MASK) {
+ TCGv_i32 t_size = tcg_const_i32(1 << ot);
+ TCGv t_next = tcg_const_tl(s->pc - s->cs_base);
+
+ gen_helper_bpt_io(cpu_env, t_port, t_size, t_next);
+ tcg_temp_free_i32(t_size);
+ tcg_temp_free(t_next);
+ }
+}
+
+
static inline void gen_ins(DisasContext *s, TCGMemOp ot)
{
if (s->tb->cflags & CF_USE_ICOUNT) {
@@ -1170,6 +1183,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp ot)
gen_op_st_v(s, ot, cpu_T[0], cpu_A0);
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_EDI);
+ gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
}
@@ -1187,9 +1201,9 @@ static inline void gen_outs(DisasContext *s, TCGMemOp ot)
tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
-
gen_op_movl_T0_Dshift(ot);
gen_op_add_reg_T0(s->aflag, R_ESI);
+ gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
}
@@ -6269,6 +6283,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_movi_i32(cpu_tmp2_i32, val);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
+ gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@@ -6289,6 +6304,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_movi_i32(cpu_tmp2_i32, val);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
+ gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@@ -6306,6 +6322,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
gen_op_mov_reg_v(ot, R_EAX, cpu_T[1]);
+ gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
@@ -6325,6 +6342,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
+ gen_bpt_io(s, cpu_tmp2_i32, ot);
if (s->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
gen_jmp(s, s->pc - s->cs_base);
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints Eduardo Habkost
@ 2015-10-19 17:30 ` Eduardo Habkost
2015-10-19 17:46 ` Richard Henderson
0 siblings, 1 reply; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-19 17:30 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
On Fri, Oct 16, 2015 at 01:23:36PM -0300, Eduardo Habkost wrote:
> From: Richard Henderson <rth@twiddle.net>
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> Changes v1 -> v2:
> * Rebase on top of new version of "Re-introduce optimal breakpoint
> removal"
> ---
> target-i386/bpt_helper.c | 98 +++++++++++++++++++++++++++++++++++-------------
> target-i386/cpu.h | 2 +
> target-i386/helper.h | 1 +
> target-i386/translate.c | 20 +++++++++-
> 4 files changed, 93 insertions(+), 28 deletions(-)
>
> diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
> index 0563abd..00f3942 100644
> --- a/target-i386/bpt_helper.c
> +++ b/target-i386/bpt_helper.c
> @@ -49,60 +49,72 @@ static inline int hw_breakpoint_len(unsigned long dr7, int index)
> return (len == 2) ? 8 : len + 1;
> }
>
> -static void hw_breakpoint_insert(CPUX86State *env, int index)
> +static int hw_breakpoint_insert(CPUX86State *env, int index)
> {
> CPUState *cs = CPU(x86_env_get_cpu(env));
> - int type = 0, err = 0;
> + target_ulong dr7 = env->dr[7];
> + target_ulong drN = env->dr[index];
> + int err = 0;
>
> - switch (hw_breakpoint_type(env->dr[7], index)) {
> + switch (hw_breakpoint_type(dr7, index)) {
> case DR7_TYPE_BP_INST:
> - if (hw_breakpoint_enabled(env->dr[7], index)) {
> - err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,
> + if (hw_breakpoint_enabled(dr7, index)) {
> + err = cpu_breakpoint_insert(cs, drN, BP_CPU,
> &env->cpu_breakpoint[index]);
> }
> break;
> - case DR7_TYPE_DATA_WR:
> - type = BP_CPU | BP_MEM_WRITE;
> - break;
> +
> case DR7_TYPE_IO_RW:
> - /* No support for I/O watchpoints yet */
> + /* Notice when we should enable calls to bpt_io. */
> + return (hw_breakpoint_enabled(env->dr[7], index)
> + ? HF_IOBPT_MASK : 0);
checkpatch.pl error:
ERROR: return is not a function, parentheses are not required
#57: FILE: target-i386/bpt_helper.c:69:
+ return (hw_breakpoint_enabled(env->dr[7], index)
total: 1 errors, 0 warnings, 242 lines checked
I will fix it in v3.
--
Eduardo
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints
2015-10-19 17:30 ` Eduardo Habkost
@ 2015-10-19 17:46 ` Richard Henderson
2015-10-19 17:57 ` Eduardo Habkost
0 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2015-10-19 17:46 UTC (permalink / raw)
To: Eduardo Habkost, qemu-devel, Paolo Bonzini
On 10/19/2015 07:30 AM, Eduardo Habkost wrote:
>> >+ /* Notice when we should enable calls to bpt_io. */
>> >+ return (hw_breakpoint_enabled(env->dr[7], index)
>> >+ ? HF_IOBPT_MASK : 0);
> checkpatch.pl error:
>
> ERROR: return is not a function, parentheses are not required
> #57: FILE: target-i386/bpt_helper.c:69:
> + return (hw_breakpoint_enabled(env->dr[7], index)
>
> total: 1 errors, 0 warnings, 242 lines checked
>
> I will fix it in v3.
In this case checkpatch is wrong, imo. The parenthesis are not there to "make
return a function", but to make the multi-line expression indent properly.
r~
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints
2015-10-19 17:46 ` Richard Henderson
@ 2015-10-19 17:57 ` Eduardo Habkost
2015-10-20 12:04 ` Paolo Bonzini
0 siblings, 1 reply; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-19 17:57 UTC (permalink / raw)
To: Richard Henderson; +Cc: Paolo Bonzini, qemu-devel
On Mon, Oct 19, 2015 at 07:46:51AM -1000, Richard Henderson wrote:
> On 10/19/2015 07:30 AM, Eduardo Habkost wrote:
> >>>+ /* Notice when we should enable calls to bpt_io. */
> >>>+ return (hw_breakpoint_enabled(env->dr[7], index)
> >>>+ ? HF_IOBPT_MASK : 0);
> >checkpatch.pl error:
> >
> > ERROR: return is not a function, parentheses are not required
> > #57: FILE: target-i386/bpt_helper.c:69:
> > + return (hw_breakpoint_enabled(env->dr[7], index)
> >
> > total: 1 errors, 0 warnings, 242 lines checked
> >
> >I will fix it in v3.
>
> In this case checkpatch is wrong, imo. The parenthesis are not there to
> "make return a function", but to make the multi-line expression indent
> properly.
I understand if one thinks the expression looks better with the parenthesis,
but I fail to see why they are needed to indent the expression properly.
For reference, this is the change I have made in v3:
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index 0fbdc03..dac1b1a 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -66,8 +66,8 @@ static int hw_breakpoint_insert(CPUX86State *env, int index)
case DR7_TYPE_IO_RW:
/* Notice when we should enable calls to bpt_io. */
- return (hw_breakpoint_enabled(env->dr[7], index)
- ? HF_IOBPT_MASK : 0);
+ return hw_breakpoint_enabled(env->dr[7], index)
+ ? HF_IOBPT_MASK : 0;
case DR7_TYPE_DATA_WR:
if (hw_breakpoint_enabled(dr7, index)) {
--
Eduardo
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints
2015-10-19 17:57 ` Eduardo Habkost
@ 2015-10-20 12:04 ` Paolo Bonzini
0 siblings, 0 replies; 17+ messages in thread
From: Paolo Bonzini @ 2015-10-20 12:04 UTC (permalink / raw)
To: Eduardo Habkost, Richard Henderson; +Cc: qemu-devel
On 19/10/2015 19:57, Eduardo Habkost wrote:
> On Mon, Oct 19, 2015 at 07:46:51AM -1000, Richard Henderson wrote:
>> On 10/19/2015 07:30 AM, Eduardo Habkost wrote:
>>>>> + /* Notice when we should enable calls to bpt_io. */
>>>>> + return (hw_breakpoint_enabled(env->dr[7], index)
>>>>> + ? HF_IOBPT_MASK : 0);
>>> checkpatch.pl error:
>>>
>>> ERROR: return is not a function, parentheses are not required
>>> #57: FILE: target-i386/bpt_helper.c:69:
>>> + return (hw_breakpoint_enabled(env->dr[7], index)
>>>
>>> total: 1 errors, 0 warnings, 242 lines checked
>>>
>>> I will fix it in v3.
>>
>> In this case checkpatch is wrong, imo. The parenthesis are not there to
>> "make return a function", but to make the multi-line expression indent
>> properly.
>
> I understand if one thinks the expression looks better with the parenthesis,
> but I fail to see why they are needed to indent the expression properly.
Because Emacs indents this:
> + return hw_breakpoint_enabled(env->dr[7], index)
> + ? HF_IOBPT_MASK : 0;
with the ? under the second "r" of "return", while it indents this as
written:
> - return (hw_breakpoint_enabled(env->dr[7], index)
> - ? HF_IOBPT_MASK : 0);
Another random example:
static bool sdl_check_format(DisplayChangeListener *dcl,
pixman_format_code_t format)
{
/*
* We let SDL convert for us a few more formats than,
* the native ones. Thes are the ones I have tested.
*/
return (format == PIXMAN_x8r8g8b8 ||
format == PIXMAN_b8g8r8x8 ||
format == PIXMAN_x1r5g5b5 ||
format == PIXMAN_r5g6b5);
}
There's no unanimity though, so your v3 is okay too.
Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Qemu-devel] [PATCH v2 7/9] target-i386: Check CR4[DE] for processing DR4/DR5
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
` (5 preceding siblings ...)
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 6/9] target-i386: Handle I/O breakpoints Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 8/9] target-i386: Ensure always-1 bits on DR6 can't be cleared Eduardo Habkost
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 9/9] target-i386: Add DE to TCG_FEATURES Eduardo Habkost
8 siblings, 0 replies; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
From: Richard Henderson <rth@twiddle.net>
Introduce helper_get_dr so that we don't have to put CR4[DE]
into the scarce HFLAGS resource. At the same time, rename
helper_movl_drN_T0 to helper_set_dr and set the helper flags.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/bpt_helper.c | 46 +++++++++++++++++++++++++++++++++++++++++-----
target-i386/cpu.h | 2 +-
target-i386/helper.h | 3 ++-
target-i386/translate.c | 10 ++++++----
4 files changed, 50 insertions(+), 11 deletions(-)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index 00f3942..3cb4a09 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -241,10 +241,11 @@ void helper_single_step(CPUX86State *env)
raise_exception(env, EXCP01_DB);
}
-void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
+void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
{
#ifndef CONFIG_USER_ONLY
- if (reg < 4) {
+ switch (reg) {
+ case 0: case 1: case 2: case 3:
if (hw_breakpoint_enabled(env->dr[7], reg)
&& hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
hw_breakpoint_remove(env, reg);
@@ -253,14 +254,49 @@ void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
} else {
env->dr[reg] = t0;
}
- } else if (reg == 7) {
+ return;
+ case 4:
+ if (env->cr[4] & CR4_DE_MASK) {
+ break;
+ }
+ /* fallthru */
+ case 6:
+ env->dr[6] = t0;
+ return;
+ case 5:
+ if (env->cr[4] & CR4_DE_MASK) {
+ break;
+ }
+ /* fallthru */
+ case 7:
cpu_x86_update_dr7(env, t0);
- } else {
- env->dr[reg] = t0;
+ return;
}
+ raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
#endif
}
+target_ulong helper_get_dr(CPUX86State *env, int reg)
+{
+ switch (reg) {
+ case 0: case 1: case 2: case 3: case 6: case 7:
+ return env->dr[reg];
+ case 4:
+ if (env->cr[4] & CR4_DE_MASK) {
+ break;
+ } else {
+ return env->dr[6];
+ }
+ case 5:
+ if (env->cr[4] & CR4_DE_MASK) {
+ break;
+ } else {
+ return env->dr[7];
+ }
+ }
+ raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
+}
+
/* Check if Port I/O is trapped by a breakpoint. */
void helper_bpt_io(CPUX86State *env, uint32_t port,
uint32_t size, target_ulong next_eip)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 649d54a..f4654f2 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -919,7 +919,7 @@ typedef struct CPUX86State {
int error_code;
int exception_is_int;
target_ulong exception_next_eip;
- target_ulong dr[8]; /* debug registers */
+ target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
union {
struct CPUBreakpoint *cpu_breakpoint[4];
struct CPUWatchpoint *cpu_watchpoint[4];
diff --git a/target-i386/helper.h b/target-i386/helper.h
index e9858c0..ecfcfd1 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -40,7 +40,8 @@ DEF_HELPER_2(read_crN, tl, env, int)
DEF_HELPER_3(write_crN, void, env, int, tl)
DEF_HELPER_2(lmsw, void, env, tl)
DEF_HELPER_1(clts, void, env)
-DEF_HELPER_3(movl_drN_T0, void, env, int, tl)
+DEF_HELPER_FLAGS_3(set_dr, TCG_CALL_NO_WG, void, env, int, tl)
+DEF_HELPER_FLAGS_2(get_dr, TCG_CALL_NO_WG, tl, env, int)
DEF_HELPER_2(invlpg, void, env, tl)
DEF_HELPER_4(enter_level, void, env, int, int, tl)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ceed4d1..764b1e4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7627,18 +7627,20 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
ot = MO_64;
else
ot = MO_32;
- /* XXX: do it dynamically with CR4.DE bit */
- if (reg == 4 || reg == 5 || reg >= 8)
+ if (reg >= 8) {
goto illegal_op;
+ }
if (b & 2) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
gen_op_mov_v_reg(ot, cpu_T[0], rm);
- gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
+ tcg_gen_movi_i32(cpu_tmp2_i32, reg);
+ gen_helper_set_dr(cpu_env, cpu_tmp2_i32, cpu_T[0]);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
- tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
+ tcg_gen_movi_i32(cpu_tmp2_i32, reg);
+ gen_helper_get_dr(cpu_T[0], cpu_env, cpu_tmp2_i32);
gen_op_mov_reg_v(ot, rm, cpu_T[0]);
}
}
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH v2 8/9] target-i386: Ensure always-1 bits on DR6 can't be cleared
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
` (6 preceding siblings ...)
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 7/9] target-i386: Check CR4[DE] for processing DR4/DR5 Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-18 23:05 ` Richard Henderson
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 9/9] target-i386: Add DE to TCG_FEATURES Eduardo Habkost
8 siblings, 1 reply; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
Bits 4-11 and 16-31 on DR6 are documented as always 1, so ensure they
can't be cleared by software.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/bpt_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/bpt_helper.c b/target-i386/bpt_helper.c
index 3cb4a09..0fbdc03 100644
--- a/target-i386/bpt_helper.c
+++ b/target-i386/bpt_helper.c
@@ -261,7 +261,7 @@ void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
}
/* fallthru */
case 6:
- env->dr[6] = t0;
+ env->dr[6] = t0 | DR6_FIXED_1;
return;
case 5:
if (env->cr[4] & CR4_DE_MASK) {
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Qemu-devel] [PATCH v2 9/9] target-i386: Add DE to TCG_FEATURES
2015-10-16 16:23 [Qemu-devel] [PATCH v2 0/9] target-i386: Implement debug extensions Eduardo Habkost
` (7 preceding siblings ...)
2015-10-16 16:23 ` [Qemu-devel] [PATCH v2 8/9] target-i386: Ensure always-1 bits on DR6 can't be cleared Eduardo Habkost
@ 2015-10-16 16:23 ` Eduardo Habkost
2015-10-18 23:06 ` Richard Henderson
8 siblings, 1 reply; 17+ messages in thread
From: Eduardo Habkost @ 2015-10-16 16:23 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini, Richard Henderson
Now DE is supported by TCG so it can be enabled in CPUID bits.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target-i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 05d7f26..5fe49b5 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -312,7 +312,7 @@ static const char *cpuid_6_feature_name[] = {
CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
- CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
/* partly implemented:
CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
/* missing:
--
2.1.0
^ permalink raw reply related [flat|nested] 17+ messages in thread