From: Pierrick Bouvier <pierrick.bouvier@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract
Date: Tue, 15 Apr 2025 14:50:12 -0700 [thread overview]
Message-ID: <56284764-090d-410b-a2d3-ea0c4d63380f@linaro.org> (raw)
In-Reply-To: <20250415192515.232910-94-richard.henderson@linaro.org>
On 4/15/25 12:24, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/tcg.c | 20 +++++++++
> tcg/aarch64/tcg-target.c.inc | 28 +++++++-----
> tcg/arm/tcg-target.c.inc | 23 +++++-----
> tcg/i386/tcg-target.c.inc | 77 +++++++++++++++++---------------
> tcg/loongarch64/tcg-target.c.inc | 33 +++++++-------
> tcg/mips/tcg-target.c.inc | 35 +++++++--------
> tcg/ppc/tcg-target.c.inc | 35 +++++++--------
> tcg/riscv/tcg-target.c.inc | 54 +++++++++++-----------
> tcg/s390x/tcg-target.c.inc | 14 +++---
> tcg/sparc64/tcg-target.c.inc | 16 ++++---
> tcg/tci/tcg-target.c.inc | 8 ++--
> 11 files changed, 191 insertions(+), 152 deletions(-)
>
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 40c67dbc6f..3f81dce074 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -1013,6 +1013,12 @@ typedef struct TCGOutOpDivRem {
> TCGReg a0, TCGReg a1, TCGReg a4);
> } TCGOutOpDivRem;
>
> +typedef struct TCGOutOpExtract {
> + TCGOutOp base;
> + void (*out_rr)(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len);
> +} TCGOutOpExtract;
> +
> typedef struct TCGOutOpMovcond {
> TCGOutOp base;
> void (*out)(TCGContext *s, TCGType type, TCGCond cond,
> @@ -1085,6 +1091,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
> OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2),
> OUTOP(INDEX_op_divu2, TCGOutOpDivRem, outop_divu2),
> OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
> + OUTOP(INDEX_op_extract_i32, TCGOutOpExtract, outop_extract),
> + OUTOP(INDEX_op_extract_i64, TCGOutOpExtract, outop_extract),
> OUTOP(INDEX_op_movcond, TCGOutOpMovcond, outop_movcond),
> OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
> OUTOP(INDEX_op_muls2, TCGOutOpMul2, outop_muls2),
> @@ -5508,6 +5516,18 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
> }
> break;
>
> + case INDEX_op_extract_i32:
> + case INDEX_op_extract_i64:
> + {
> + const TCGOutOpExtract *out =
> + container_of(all_outop[op->opc], TCGOutOpExtract, base);
> +
> + tcg_debug_assert(!const_args[1]);
> + out->out_rr(s, type, new_args[0], new_args[1],
> + new_args[2], new_args[3]);
> + }
> + break;
> +
> case INDEX_op_muls2:
> case INDEX_op_mulu2:
> {
> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
> index 79c0e2e097..6c9d6094a2 100644
> --- a/tcg/aarch64/tcg-target.c.inc
> +++ b/tcg/aarch64/tcg-target.c.inc
> @@ -2567,6 +2567,22 @@ static const TCGOutOpMovcond outop_movcond = {
> .out = tgen_movcond,
> };
>
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len)
> +{
> + if (ofs == 0) {
> + uint64_t mask = MAKE_64BIT_MASK(0, len);
> + tcg_out_logicali(s, I3404_ANDI, type, a0, a1, mask);
> + } else {
> + tcg_out_ubfm(s, type, a0, a1, ofs, ofs + len - 1);
> + }
> +}
> +
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
> +
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
> const TCGArg args[TCG_MAX_OP_ARGS],
> const int const_args[TCG_MAX_OP_ARGS])
> @@ -2652,16 +2668,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
> tcg_out_dep(s, ext, a0, a2, args[3], args[4]);
> break;
>
> - case INDEX_op_extract_i64:
> - case INDEX_op_extract_i32:
> - if (a2 == 0) {
> - uint64_t mask = MAKE_64BIT_MASK(0, args[3]);
> - tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, mask);
> - } else {
> - tcg_out_ubfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
> - }
> - break;
> -
> case INDEX_op_sextract_i64:
> case INDEX_op_sextract_i32:
> tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
> @@ -3167,8 +3173,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> - case INDEX_op_extract_i32:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index 3bbc28c63c..bc060b20f2 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -981,19 +981,19 @@ static void tcg_out_deposit(TCGContext *s, ARMCond cond, TCGReg rd,
> | (ofs << 7) | ((ofs + len - 1) << 16));
> }
>
> -static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd,
> - TCGReg rn, int ofs, int len)
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg rd, TCGReg rn,
> + unsigned ofs, unsigned len)
> {
> /* According to gcc, AND can be faster. */
> if (ofs == 0 && len <= 8) {
> - tcg_out_dat_imm(s, cond, ARITH_AND, rd, rn,
> + tcg_out_dat_imm(s, COND_AL, ARITH_AND, rd, rn,
> encode_imm_nofail((1 << len) - 1));
> return;
> }
>
> if (use_armv7_instructions) {
> /* ubfx */
> - tcg_out32(s, 0x07e00050 | (cond << 28) | (rd << 12) | rn
> + tcg_out32(s, 0x07e00050 | (COND_AL << 28) | (rd << 12) | rn
> | (ofs << 7) | ((len - 1) << 16));
> return;
> }
> @@ -1002,17 +1002,24 @@ static void tcg_out_extract(TCGContext *s, ARMCond cond, TCGReg rd,
> switch (len) {
> case 8:
> /* uxtb */
> - tcg_out32(s, 0x06ef0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
> + tcg_out32(s, 0x06ef0070 | (COND_AL << 28) |
> + (rd << 12) | (ofs << 7) | rn);
> break;
> case 16:
> /* uxth */
> - tcg_out32(s, 0x06ff0070 | (cond << 28) | (rd << 12) | (ofs << 7) | rn);
> + tcg_out32(s, 0x06ff0070 | (COND_AL << 28) |
> + (rd << 12) | (ofs << 7) | rn);
> break;
> default:
> g_assert_not_reached();
> }
> }
>
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
> +
> static void tcg_out_sextract(TCGContext *s, ARMCond cond, TCGReg rd,
> TCGReg rn, int ofs, int len)
> {
> @@ -2392,9 +2399,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_deposit(s, COND_AL, args[0], args[2],
> args[3], args[4], const_args[2]);
> break;
> - case INDEX_op_extract_i32:
> - tcg_out_extract(s, COND_AL, args[0], args[1], args[2], args[3]);
> - break;
> case INDEX_op_sextract_i32:
> tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
> break;
> @@ -2444,7 +2448,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld16u_i32:
> case INDEX_op_ld16s_i32:
> case INDEX_op_ld_i32:
> - case INDEX_op_extract_i32:
> case INDEX_op_sextract_i32:
> return C_O1_I1(r, r);
>
> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
> index 347e01c076..b26c93bdb1 100644
> --- a/tcg/i386/tcg-target.c.inc
> +++ b/tcg/i386/tcg-target.c.inc
> @@ -3138,6 +3138,47 @@ static const TCGOutOpUnary outop_not = {
> .out_rr = tgen_not,
> };
>
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len)
> +{
> + if (ofs == 0) {
> + switch (len) {
> + case 8:
> + tcg_out_ext8u(s, a0, a1);
> + return;
> + case 16:
> + tcg_out_ext16u(s, a0, a1);
> + return;
> + case 32:
> + tcg_out_ext32u(s, a0, a1);
> + return;
> + }
> + } else if (TCG_TARGET_REG_BITS == 64 && ofs + len == 32) {
> + /* This is a 32-bit zero-extending right shift. */
> + tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
> + tcg_out_shifti(s, SHIFT_SHR, a0, ofs);
> + return;
> + } else if (ofs == 8 && len == 8) {
> + /*
> + * On the off-chance that we can use the high-byte registers.
> + * Otherwise we emit the same ext16 + shift pattern that we
> + * would have gotten from the normal tcg-op.c expansion.
> + */
> + if (a1 < 4 && (TCG_TARGET_REG_BITS == 32 || a0 < 8)) {
> + tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4);
> + } else {
> + tcg_out_ext16u(s, a0, a1);
> + tcg_out_shifti(s, SHIFT_SHR, a0, 8);
> + }
> + return;
> + }
> + g_assert_not_reached();
> +}
> +
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
>
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const TCGArg args[TCG_MAX_OP_ARGS],
> @@ -3328,40 +3369,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_extract_i64:
> - if (a2 + args[3] == 32) {
> - if (a2 == 0) {
> - tcg_out_ext32u(s, a0, a1);
> - break;
> - }
> - /* This is a 32-bit zero-extending right shift. */
> - tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
> - tcg_out_shifti(s, SHIFT_SHR, a0, a2);
> - break;
> - }
> - /* FALLTHRU */
> - case INDEX_op_extract_i32:
> - if (a2 == 0 && args[3] == 8) {
> - tcg_out_ext8u(s, a0, a1);
> - } else if (a2 == 0 && args[3] == 16) {
> - tcg_out_ext16u(s, a0, a1);
> - } else if (a2 == 8 && args[3] == 8) {
> - /*
> - * On the off-chance that we can use the high-byte registers.
> - * Otherwise we emit the same ext16 + shift pattern that we
> - * would have gotten from the normal tcg-op.c expansion.
> - */
> - if (a1 < 4 && a0 < 8) {
> - tcg_out_modrm(s, OPC_MOVZBL, a0, a1 + 4);
> - } else {
> - tcg_out_ext16u(s, a0, a1);
> - tcg_out_shifti(s, SHIFT_SHR, a0, 8);
> - }
> - } else {
> - g_assert_not_reached();
> - }
> - break;
> -
> case INDEX_op_sextract_i64:
> if (a2 == 0 && args[3] == 8) {
> tcg_out_ext8s(s, TCG_TYPE_I64, a0, a1);
> @@ -3994,8 +4001,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> case INDEX_op_extrl_i64_i32:
> - case INDEX_op_extract_i32:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index 25adbb0609..42983aff3b 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -1787,6 +1787,22 @@ static const TCGOutOpUnary outop_not = {
> .out_rr = tgen_not,
> };
>
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len)
> +{
> + if (ofs == 0 && len <= 12) {
> + tcg_out_opc_andi(s, a0, a1, (1 << len) - 1);
> + } else if (type == TCG_TYPE_I32) {
> + tcg_out_opc_bstrpick_w(s, a0, a1, ofs, ofs + len - 1);
> + } else {
> + tcg_out_opc_bstrpick_d(s, a0, a1, ofs, ofs + len - 1);
> + }
> +}
> +
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
>
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const TCGArg args[TCG_MAX_OP_ARGS],
> @@ -1816,21 +1832,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_opc_srai_d(s, a0, a1, 32);
> break;
>
> - case INDEX_op_extract_i32:
> - if (a2 == 0 && args[3] <= 12) {
> - tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1);
> - } else {
> - tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
> - }
> - break;
> - case INDEX_op_extract_i64:
> - if (a2 == 0 && args[3] <= 12) {
> - tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1);
> - } else {
> - tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
> - }
> - break;
> -
> case INDEX_op_sextract_i64:
> if (a2 + args[3] == 32) {
> if (a2 == 0) {
> @@ -2455,8 +2456,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extrl_i64_i32:
> case INDEX_op_extrh_i64_i32:
> case INDEX_op_ext_i32_i64:
> - case INDEX_op_extract_i32:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> case INDEX_op_ld8s_i32:
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index baaf0e416b..dbb4b9355d 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -2203,6 +2203,23 @@ static const TCGOutOpUnary outop_not = {
> .out_rr = tgen_not,
> };
>
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len)
> +{
> + if (ofs == 0 && len <= 16) {
> + tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << len) - 1);
> + } else if (type == TCG_TYPE_I32) {
> + tcg_out_opc_bf(s, OPC_EXT, a0, a1, len - 1, ofs);
> + } else {
> + tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU,
> + a0, a1, len - 1, ofs);
> + }
> +}
> +
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
>
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const TCGArg args[TCG_MAX_OP_ARGS],
> @@ -2286,22 +2303,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> args[3] + args[4] - 1, args[3]);
> break;
>
> - case INDEX_op_extract_i32:
> - if (a2 == 0 && args[3] <= 16) {
> - tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
> - } else {
> - tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
> - }
> - break;
> - case INDEX_op_extract_i64:
> - if (a2 == 0 && args[3] <= 16) {
> - tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1);
> - } else {
> - tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU,
> - a0, a1, args[3] - 1, a2);
> - }
> - break;
> -
> case INDEX_op_sextract_i64:
> if (a2 == 0 && args[3] == 32) {
> tcg_out_ext32s(s, a0, a1);
> @@ -2375,7 +2376,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld16u_i32:
> case INDEX_op_ld16s_i32:
> case INDEX_op_ld_i32:
> - case INDEX_op_extract_i32:
> case INDEX_op_sextract_i32:
> case INDEX_op_ld8u_i64:
> case INDEX_op_ld8s_i64:
> @@ -2388,7 +2388,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extu_i32_i64:
> case INDEX_op_extrl_i64_i32:
> case INDEX_op_extrh_i64_i32:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
>
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index 083137d211..a8558a47b7 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -3417,6 +3417,23 @@ static const TCGOutOpUnary outop_not = {
> .out_rr = tgen_not,
> };
>
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len)
> +{
> + if (ofs == 0 && len <= 16) {
> + tgen_andi(s, TCG_TYPE_I32, a0, a1, (1 << len) - 1);
> + } else if (type == TCG_TYPE_I32) {
> + tcg_out_rlw(s, RLWINM, a0, a1, 32 - ofs, 32 - len, 31);
> + } else {
> + tcg_out_rld(s, RLDICL, a0, a1, 64 - ofs, 64 - len);
> + }
> +}
> +
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
> +
>
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const TCGArg args[TCG_MAX_OP_ARGS],
> @@ -3538,22 +3555,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - case INDEX_op_extract_i32:
> - if (args[2] == 0 && args[3] <= 16) {
> - tcg_out32(s, ANDI | SAI(args[1], args[0], (1 << args[3]) - 1));
> - break;
> - }
> - tcg_out_rlw(s, RLWINM, args[0], args[1],
> - 32 - args[2], 32 - args[3], 31);
> - break;
> - case INDEX_op_extract_i64:
> - if (args[2] == 0 && args[3] <= 16) {
> - tcg_out32(s, ANDI | SAI(args[1], args[0], (1 << args[3]) - 1));
> - break;
> - }
> - tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
> - break;
> -
> case INDEX_op_sextract_i64:
> if (args[2] + args[3] == 32) {
> if (args[2] == 0) {
> @@ -4255,7 +4256,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld16u_i32:
> case INDEX_op_ld16s_i32:
> case INDEX_op_ld_i32:
> - case INDEX_op_extract_i32:
> case INDEX_op_sextract_i32:
> case INDEX_op_ld8u_i64:
> case INDEX_op_ld8s_i64:
> @@ -4266,7 +4266,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 00b097d171..85d978763c 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -2472,6 +2472,34 @@ static const TCGOutOpUnary outop_not = {
> .out_rr = tgen_not,
> };
>
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len)
> +{
> + if (ofs == 0) {
> + switch (len) {
> + case 16:
> + tcg_out_ext16u(s, a0, a1);
> + return;
> + case 32:
> + tcg_out_ext32u(s, a0, a1);
> + return;
> + }
> + }
> + if (ofs + len == 32) {
> + tgen_shli(s, TCG_TYPE_I32, a0, a1, ofs);
> + return;
> + }
> + if (len == 1) {
> + tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, ofs);
> + return;
> + }
> + g_assert_not_reached();
> +}
> +
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
>
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const TCGArg args[TCG_MAX_OP_ARGS],
> @@ -2572,30 +2600,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_mb(s, a0);
> break;
>
> - case INDEX_op_extract_i64:
> - if (a2 + args[3] == 32) {
> - if (a2 == 0) {
> - tcg_out_ext32u(s, a0, a1);
> - } else {
> - tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
> - }
> - break;
> - }
> - /* FALLTHRU */
> - case INDEX_op_extract_i32:
> - switch (args[3]) {
> - case 1:
> - tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, a2);
> - break;
> - case 16:
> - tcg_debug_assert(a2 == 0);
> - tcg_out_ext16u(s, a0, a1);
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - break;
> -
> case INDEX_op_sextract_i64:
> if (a2 + args[3] == 32) {
> if (a2 == 0) {
> @@ -2867,8 +2871,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_extrl_i64_i32:
> case INDEX_op_extrh_i64_i32:
> case INDEX_op_ext_i32_i64:
> - case INDEX_op_extract_i32:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index 2ed288cfe0..96e2dc0ad5 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -1563,8 +1563,8 @@ static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
> tcg_out_risbg(s, dest, src, msb, lsb, ofs, z);
> }
>
> -static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
> - int ofs, int len)
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg dest,
> + TCGReg src, unsigned ofs, unsigned len)
> {
> if (ofs == 0) {
> switch (len) {
> @@ -1582,6 +1582,11 @@ static void tgen_extract(TCGContext *s, TCGReg dest, TCGReg src,
> tcg_out_risbg(s, dest, src, 64 - len, 63, 64 - ofs, 1);
> }
>
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
> +
> static void tgen_sextract(TCGContext *s, TCGReg dest, TCGReg src,
> int ofs, int len)
> {
> @@ -2975,9 +2980,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> }
> break;
>
> - OP_32_64(extract):
> - tgen_extract(s, args[0], args[1], args[2], args[3]);
> - break;
> OP_32_64(sextract):
> tgen_sextract(s, args[0], args[1], args[2], args[3]);
> break;
> @@ -3470,8 +3472,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
>
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> - case INDEX_op_extract_i32:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index 96ffba9af6..cba1dd009c 100644
> --- a/tcg/sparc64/tcg-target.c.inc
> +++ b/tcg/sparc64/tcg-target.c.inc
> @@ -1757,6 +1757,17 @@ static const TCGOutOpUnary outop_not = {
> .out_rr = tgen_not,
> };
>
> +static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,
> + unsigned ofs, unsigned len)
> +{
> + tcg_debug_assert(ofs + len == 32);
> + tcg_out_arithi(s, a0, a1, ofs, SHIFT_SRL);
> +}
> +
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tgen_extract,
> +};
>
> static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> const TCGArg args[TCG_MAX_OP_ARGS],
> @@ -1857,10 +1868,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_mb(s, a0);
> break;
>
> - case INDEX_op_extract_i64:
> - tcg_debug_assert(a2 + args[3] == 32);
> - tcg_out_arithi(s, a0, a1, a2, SHIFT_SRL);
> - break;
> case INDEX_op_sextract_i64:
> tcg_debug_assert(a2 + args[3] == 32);
> tcg_out_arithi(s, a0, a1, a2, SHIFT_SRA);
> @@ -1897,7 +1904,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i64:
> case INDEX_op_qemu_ld_i32:
> case INDEX_op_qemu_ld_i64:
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 4fc857ad35..d8cf5d237b 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -57,8 +57,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
> case INDEX_op_ld_i64:
> case INDEX_op_ext_i32_i64:
> case INDEX_op_extu_i32_i64:
> - case INDEX_op_extract_i32:
> - case INDEX_op_extract_i64:
> case INDEX_op_sextract_i32:
> case INDEX_op_sextract_i64:
> return C_O1_I1(r, r);
> @@ -444,6 +442,11 @@ static void tcg_out_extract(TCGContext *s, TCGType type, TCGReg rd,
> tcg_out_op_rrbb(s, opc, rd, rs, pos, len);
> }
>
> +static const TCGOutOpExtract outop_extract = {
> + .base.static_constraint = C_O1_I1(r, r),
> + .out_rr = tcg_out_extract,
> +};
> +
> static void tcg_out_sextract(TCGContext *s, TCGType type, TCGReg rd,
> TCGReg rs, unsigned pos, unsigned len)
> {
> @@ -1078,7 +1081,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
> tcg_out_op_rrrbb(s, opc, args[0], args[1], args[2], args[3], args[4]);
> break;
>
> - CASE_32_64(extract) /* Optional (TCG_TARGET_HAS_extract_*). */
> CASE_32_64(sextract) /* Optional (TCG_TARGET_HAS_sextract_*). */
> tcg_out_op_rrbb(s, opc, args[0], args[1], args[2], args[3]);
> break;
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
next prev parent reply other threads:[~2025-04-15 21:50 UTC|newest]
Thread overview: 316+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 19:22 [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Richard Henderson
2025-04-15 19:22 ` [PATCH v4 001/163] tcg: Add all_outop[] Richard Henderson
2025-04-15 19:22 ` [PATCH v4 002/163] tcg: Use extract2 for cross-word 64-bit extract on 32-bit host Richard Henderson
2025-04-15 19:22 ` [PATCH v4 003/163] tcg: Remove INDEX_op_ext{8,16,32}* Richard Henderson
2025-04-15 19:22 ` [PATCH v4 004/163] tcg: Merge INDEX_op_mov_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 005/163] tcg: Convert add to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 006/163] tcg: Merge INDEX_op_add_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 007/163] tcg: Convert and to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 008/163] tcg: Merge INDEX_op_and_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 009/163] tcg/optimize: Fold andc with immediate to and Richard Henderson
2025-04-15 19:22 ` [PATCH v4 010/163] tcg/optimize: Emit add r, r, -1 in fold_setcond_tst_pow2 Richard Henderson
2025-04-15 19:22 ` [PATCH v4 011/163] tcg: Convert andc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 012/163] tcg: Merge INDEX_op_andc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 013/163] tcg: Convert or to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 014/163] tcg: Merge INDEX_op_or_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 015/163] tcg/optimize: Fold orc with immediate to or Richard Henderson
2025-04-15 19:22 ` [PATCH v4 016/163] tcg: Convert orc to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 017/163] tcg: Merge INDEX_op_orc_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 018/163] tcg: Convert xor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 019/163] tcg: Merge INDEX_op_xor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 020/163] tcg/optimize: Fold eqv with immediate to xor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 021/163] tcg: Convert eqv to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 022/163] tcg: Merge INDEX_op_eqv_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 023/163] tcg: Convert nand to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 024/163] tcg: Merge INDEX_op_nand_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 025/163] tcg/loongarch64: Do not accept constant argument to nor Richard Henderson
2025-04-15 19:22 ` [PATCH v4 026/163] tcg: Convert nor to TCGOutOpBinary Richard Henderson
2025-04-15 19:22 ` [PATCH v4 027/163] tcg: Merge INDEX_op_nor_{i32,i64} Richard Henderson
2025-04-15 19:22 ` [PATCH v4 028/163] tcg/arm: Fix constraints for sub Richard Henderson
2025-04-15 19:23 ` [PATCH v4 029/163] tcg: Convert sub to TCGOutOpSubtract Richard Henderson
2025-04-15 21:00 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 030/163] tcg: Merge INDEX_op_sub_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 031/163] tcg: Convert neg to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 032/163] tcg: Merge INDEX_op_neg_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 033/163] tcg: Convert not to TCGOutOpUnary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 034/163] tcg: Merge INDEX_op_not_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 035/163] tcg: Convert mul to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 036/163] tcg: Merge INDEX_op_mul_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 037/163] tcg: Convert muluh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 038/163] tcg: Merge INDEX_op_muluh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 039/163] tcg: Convert mulsh to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 040/163] tcg: Merge INDEX_op_mulsh_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 041/163] tcg: Convert div to TCGOutOpBinary Richard Henderson
2025-04-15 21:02 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 042/163] tcg: Merge INDEX_op_div_{i32,i64} Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-22 15:27 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 043/163] tcg: Convert divu to TCGOutOpBinary Richard Henderson
2025-04-15 21:04 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 044/163] tcg: Merge INDEX_op_divu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 045/163] tcg: Convert div2 to TCGOutOpDivRem Richard Henderson
2025-04-15 19:23 ` [PATCH v4 046/163] tcg: Merge INDEX_op_div2_{i32,i64} Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 047/163] tcg: Convert divu2 to TCGOutOpDivRem Richard Henderson
2025-04-15 21:05 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 048/163] tcg: Merge INDEX_op_divu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 049/163] tcg: Convert rem to TCGOutOpBinary Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 050/163] tcg: Merge INDEX_op_rem_{i32,i64} Richard Henderson
2025-04-15 21:06 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 051/163] tcg: Convert remu to TCGOutOpBinary Richard Henderson
2025-04-15 21:07 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 052/163] tcg: Merge INDEX_op_remu_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 053/163] tcg: Convert shl to TCGOutOpBinary Richard Henderson
2025-04-15 19:23 ` [PATCH v4 054/163] tcg: Merge INDEX_op_shl_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 055/163] tcg: Convert shr to TCGOutOpBinary Richard Henderson
2025-04-15 21:08 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 056/163] tcg: Merge INDEX_op_shr_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary Richard Henderson
2025-04-15 21:09 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 058/163] tcg: Merge INDEX_op_sar_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 059/163] tcg: Do not require both rotr and rotl from the backend Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 060/163] tcg: Convert rotl, rotr to TCGOutOpBinary Richard Henderson
2025-04-15 21:10 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 061/163] tcg: Merge INDEX_op_rot{l,r}_{i32,i64} Richard Henderson
2025-04-15 21:11 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 062/163] tcg: Convert clz to TCGOutOpBinary Richard Henderson
2025-04-15 21:12 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 063/163] tcg: Merge INDEX_op_clz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 064/163] tcg: Convert ctz to TCGOutOpBinary Richard Henderson
2025-04-15 21:13 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 065/163] tcg: Merge INDEX_op_ctz_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 066/163] tcg: Convert ctpop to TCGOutOpUnary Richard Henderson
2025-04-15 21:14 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 067/163] tcg: Merge INDEX_op_ctpop_{i32,i64} Richard Henderson
2025-04-15 21:15 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 068/163] tcg: Convert muls2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 069/163] tcg: Merge INDEX_op_muls2_{i32,i64} Richard Henderson
2025-04-15 21:17 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 070/163] tcg: Convert mulu2 to TCGOutOpMul2 Richard Henderson
2025-04-15 21:18 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 071/163] tcg: Merge INDEX_op_mulu2_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 072/163] tcg/loongarch64: Support negsetcond Richard Henderson
2025-04-15 21:19 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 073/163] tcg/mips: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 074/163] tcg/tci: " Richard Henderson
2025-04-15 21:20 ` Pierrick Bouvier
2025-04-22 15:28 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 075/163] tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64} Richard Henderson
2025-04-22 15:35 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 076/163] tcg: Convert setcond, negsetcond to TCGOutOpSetcond Richard Henderson
2025-04-15 21:21 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 077/163] tcg: Merge INDEX_op_{neg}setcond_{i32,i64}` Richard Henderson
2025-04-15 21:22 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 078/163] tcg: Convert brcond to TCGOutOpBrcond Richard Henderson
2025-04-15 21:23 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 079/163] tcg: Merge INDEX_op_brcond_{i32,i64} Richard Henderson
2025-04-15 21:24 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 080/163] tcg: Convert movcond to TCGOutOpMovcond Richard Henderson
2025-04-15 21:25 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 081/163] tcg: Merge INDEX_op_movcond_{i32,i64} Richard Henderson
2025-04-15 19:23 ` [PATCH v4 082/163] tcg/ppc: Drop fallback constant loading in tcg_out_cmp Richard Henderson
2025-04-15 21:26 ` Pierrick Bouvier
2025-04-16 14:39 ` Nicholas Piggin
2025-04-16 18:57 ` Richard Henderson
2025-04-15 19:23 ` [PATCH v4 083/163] tcg/arm: Expand arguments to tcg_out_cmp2 Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 084/163] tcg/ppc: " Richard Henderson
2025-04-15 21:27 ` Pierrick Bouvier
2025-04-16 14:43 ` Nicholas Piggin
2025-04-22 15:37 ` Philippe Mathieu-Daudé
2025-04-15 19:23 ` [PATCH v4 085/163] tcg: Convert brcond2_i32 to TCGOutOpBrcond2 Richard Henderson
2025-04-15 21:37 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 086/163] tcg: Convert setcond2_i32 to TCGOutOpSetcond2 Richard Henderson
2025-04-15 21:39 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 087/163] tcg: Convert bswap16 to TCGOutOpBswap Richard Henderson
2025-04-15 21:40 ` Pierrick Bouvier
2025-04-15 19:23 ` [PATCH v4 088/163] tcg: Merge INDEX_op_bswap16_{i32,i64} Richard Henderson
2025-04-15 21:41 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 089/163] tcg: Convert bswap32 to TCGOutOpBswap Richard Henderson
2025-04-15 21:46 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 090/163] tcg: Merge INDEX_op_bswap32_{i32,i64} Richard Henderson
2025-04-15 21:47 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 091/163] tcg: Convert bswap64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 092/163] tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64 Richard Henderson
2025-04-15 21:48 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 093/163] tcg: Convert extract to TCGOutOpExtract Richard Henderson
2025-04-15 21:50 ` Pierrick Bouvier [this message]
2025-06-09 13:52 ` Andrea Bolognani
2025-06-26 16:20 ` Andrea Bolognani
2025-06-27 13:16 ` Richard Henderson
2025-06-27 14:29 ` Philippe Mathieu-Daudé
2025-06-30 12:08 ` Andrea Bolognani
2025-04-15 19:24 ` [PATCH v4 094/163] tcg: Merge INDEX_op_extract_{i32,i64} Richard Henderson
2025-04-15 21:51 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 095/163] tcg: Convert sextract to TCGOutOpExtract Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 096/163] tcg: Merge INDEX_op_sextract_{i32,i64} Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 097/163] tcg: Convert ext_i32_i64 to TCGOutOpUnary Richard Henderson
2025-04-15 21:55 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 098/163] tcg: Convert extu_i32_i64 " Richard Henderson
2025-04-15 21:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 099/163] tcg: Convert extrl_i64_i32 " Richard Henderson
2025-04-15 21:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 100/163] tcg: Convert extrh_i64_i32 " Richard Henderson
2025-04-15 21:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 101/163] tcg: Convert deposit to TCGOutOpDeposit Richard Henderson
2025-04-15 21:59 ` Pierrick Bouvier
2025-08-28 7:37 ` Michael Tokarev
2025-04-15 19:24 ` [PATCH v4 102/163] tcg/aarch64: Improve deposit Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 103/163] tcg: Merge INDEX_op_deposit_{i32,i64} Richard Henderson
2025-04-15 19:24 ` [PATCH v4 104/163] tcg: Convert extract2 to TCGOutOpExtract2 Richard Henderson
2025-04-15 22:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 105/163] tcg: Merge INDEX_op_extract2_{i32,i64} Richard Henderson
2025-04-15 22:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 106/163] tcg: Expand fallback add2 with 32-bit operations Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 107/163] tcg: Expand fallback sub2 " Richard Henderson
2025-04-15 22:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 108/163] tcg: Do not default add2/sub2_i32 for 32-bit hosts Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 109/163] tcg/mips: Drop support for add2/sub2 Richard Henderson
2025-04-15 22:04 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 110/163] tcg/riscv: " Richard Henderson
2025-04-15 22:05 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 111/163] tcg: Move i into each for loop in liveness_pass_1 Richard Henderson
2025-04-15 22:07 ` Pierrick Bouvier
2025-04-16 6:37 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 112/163] tcg: Sink def, nb_iargs, nb_oargs loads " Richard Henderson
2025-04-15 22:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 113/163] tcg: Add add/sub with carry opcodes and infrastructure Richard Henderson
2025-04-16 19:01 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 114/163] tcg: Add TCGOutOp structures for add/sub carry opcodes Richard Henderson
2025-04-16 18:56 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 115/163] tcg/optimize: Handle add/sub with " Richard Henderson
2025-04-16 19:02 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 116/163] tcg/optimize: With two const operands, prefer 0 in arg1 Richard Henderson
2025-04-16 19:03 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 117/163] tcg: Use add carry opcodes to expand add2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 118/163] tcg: Use sub carry opcodes to expand sub2 Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 119/163] tcg/i386: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 18:57 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 120/163] tcg/i386: Implement add/sub carry opcodes Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 121/163] tcg/i386: Remove support for add2/sub2 Richard Henderson
2025-04-16 18:58 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 122/163] tcg/i386: Special case addci r, 0, 0 Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 123/163] tcg: Add tcg_gen_addcio_{i32,i64,tl} Richard Henderson
2025-04-16 18:59 ` Pierrick Bouvier
2025-04-22 16:13 ` Philippe Mathieu-Daudé
2025-04-22 16:30 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 124/163] target/arm: Use tcg_gen_addcio_* for ADCS Richard Henderson
2025-04-16 19:00 ` Pierrick Bouvier
2025-04-22 16:15 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 125/163] target/hppa: Use tcg_gen_addcio_i64 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:17 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 126/163] target/microblaze: Use tcg_gen_addcio_i32 Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:28 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 127/163] target/openrisc: Use tcg_gen_addcio_* for ADDC Richard Henderson
2025-04-16 19:05 ` Pierrick Bouvier
2025-04-22 16:32 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 128/163] target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF Richard Henderson
2025-04-16 14:08 ` Nicholas Piggin
2025-04-16 19:08 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 129/163] target/s390x: Use tcg_gen_addcio_i64 for op_addc64 Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:33 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 130/163] target/sh4: Use tcg_gen_addcio_i32 for addc Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:34 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 131/163] target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 132/163] target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC Richard Henderson
2025-04-16 19:09 ` Pierrick Bouvier
2025-04-22 16:38 ` Philippe Mathieu-Daudé
2025-04-15 19:24 ` [PATCH v4 133/163] tcg/aarch64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:10 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 134/163] tcg/aarch64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:13 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 135/163] tcg/arm: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 136/163] tcg/arm: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 137/163] tcg/ppc: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:14 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 138/163] tcg/ppc: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 139/163] tcg/s390x: Honor carry_live in tcg_out_movi Richard Henderson
2025-04-16 19:15 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 140/163] tcg/s390: Add TCG_CT_CONST_N32 Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 141/163] tcg/s390x: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:16 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 142/163] tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 143/163] tcg/s390x: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:18 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 144/163] tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc Richard Henderson
2025-04-16 6:40 ` Philippe Mathieu-Daudé
2025-04-16 19:19 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 145/163] tcg/sparc64: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 146/163] tcg/sparc64: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:20 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 147/163] tcg/tci: Implement add/sub carry opcodes Richard Henderson
2025-04-16 19:36 ` Pierrick Bouvier
2025-04-15 19:24 ` [PATCH v4 148/163] tcg/tci: Remove support for add2/sub2 Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 149/163] tcg: Remove add2/sub2 opcodes Richard Henderson
2025-04-16 19:37 ` Pierrick Bouvier
2025-04-22 16:42 ` Philippe Mathieu-Daudé
2025-04-22 17:10 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 150/163] tcg: Formalize tcg_out_mb Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-22 16:44 ` Philippe Mathieu-Daudé
2025-04-15 19:25 ` [PATCH v4 151/163] tcg: Formalize tcg_out_br Richard Henderson
2025-04-16 19:38 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 152/163] tcg: Formalize tcg_out_goto_ptr Richard Henderson
2025-04-16 20:45 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 153/163] tcg: Assign TCGOP_TYPE in liveness_pass_2 Richard Henderson
2025-04-16 20:46 ` Pierrick Bouvier
2025-04-18 10:46 ` Nicholas Piggin
2025-04-21 16:28 ` Richard Henderson
2025-04-15 19:25 ` [PATCH v4 154/163] tcg: Convert ld to TCGOutOpLoad Richard Henderson
2025-04-16 20:52 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 155/163] tcg: Merge INDEX_op_ld*_{i32,i64} Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 156/163] tcg: Convert st to TCGOutOpStore Richard Henderson
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 157/163] tcg: Merge INDEX_op_st*_{i32,i64} Richard Henderson
2025-04-16 7:05 ` Philippe Mathieu-Daudé
2025-04-16 20:53 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 158/163] tcg: Stash MemOp size in TCGOP_FLAGS Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 20:54 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 159/163] tcg: Remove INDEX_op_qemu_st8_* Richard Henderson
2025-04-16 6:55 ` Philippe Mathieu-Daudé
2025-04-16 19:24 ` Richard Henderson
2025-04-16 20:55 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 160/163] tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} Richard Henderson
2025-04-16 20:56 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 161/163] tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} Richard Henderson
2025-04-16 20:57 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 162/163] tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} Richard Henderson
2025-04-16 20:58 ` Pierrick Bouvier
2025-04-15 19:25 ` [PATCH v4 163/163] tcg: Remove tcg_out_op Richard Henderson
2025-04-16 19:04 ` Pierrick Bouvier
2025-04-16 13:24 ` [PATCH v4 000/163] tcg: Convert to TCGOutOp structures Nicholas Piggin
2025-04-16 23:38 ` Pierrick Bouvier
2025-04-17 0:18 ` Richard Henderson
2025-04-17 0:49 ` Pierrick Bouvier
2025-04-17 12:02 ` BALATON Zoltan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56284764-090d-410b-a2d3-ea0c4d63380f@linaro.org \
--to=pierrick.bouvier@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).