From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46234) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpBQ0-0003fx-IF for qemu-devel@nongnu.org; Thu, 22 Oct 2015 04:40:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZpBPx-0001nh-9T for qemu-devel@nongnu.org; Thu, 22 Oct 2015 04:40:16 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50635) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZpBPx-0001nd-4Q for qemu-devel@nongnu.org; Thu, 22 Oct 2015 04:40:13 -0400 References: <1445364840-7056-1-git-send-email-lersek@redhat.com> <20151021183625.26940.67906@jljusten-ivb> From: Paolo Bonzini Message-ID: <5628A0E8.8050705@redhat.com> Date: Thu, 22 Oct 2015 10:40:08 +0200 MIME-Version: 1.0 In-Reply-To: <20151021183625.26940.67906@jljusten-ivb> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] hw/isa/lpc_ich9: inject the SMI on the VCPU that is writing to APM_CNT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jordan Justen , Laszlo Ersek , qemu-devel@nongnu.org Cc: Michael Kinney , Gerd Hoffmann , "Michael S. Tsirkin" On 21/10/2015 20:36, Jordan Justen wrote: > On 2015-10-20 11:14:00, Laszlo Ersek wrote: > > Commit 4d00636e97b7 ("ich9: Add the lpc chip", Nov 14 2012) added the > > ich9_apm_ctrl_changed() ioport write callback function such that it w= ould > > inject the SMI, in response to a write to the APM_CNT register, on th= e > > first CPU, invariably. > >=20 > > Since this register is used by guest code to trigger an SMI synchrono= usly, > > the interrupt should be injected on the VCPU that is performing the w= rite. >=20 > Why not send an SMI to *all* processors, like the real chipsets do? That's much less scalable, and more important I would have to check that SeaBIOS can handle that correctly. It probably doesn't, as it doesn't relocate SMBASEs. Paolo