* [Qemu-devel] [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
@ 2015-10-20 15:26 Chen Gang
2015-10-22 17:53 ` Richard Henderson
0 siblings, 1 reply; 3+ messages in thread
From: Chen Gang @ 2015-10-20 15:26 UTC (permalink / raw)
To: rth@twiddle.net, Peter Maydell, Chris Metcalf; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2584 bytes --]
>From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5i5j@gmail.com>
Date: Tue, 20 Oct 2015 23:19:02 +0800
Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
Originally, tilegx qemu only implement prefetch instructions in pipe x1,
did not implement them in pipe y2.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
---
target-tilegx/translate.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 34d45f8..b8ca401 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2105,6 +2105,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
unsigned srcbdest = get_SrcBDest_Y2(bundle);
const char *mnemonic;
TCGMemOp memop;
+ bool prefetch_nofault = false;
switch (OEY2(opc, mode)) {
case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
@@ -2114,6 +2115,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_UB;
mnemonic = "ld1u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_TESW;
@@ -2122,6 +2124,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_TEUW;
mnemonic = "ld2u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TESL;
@@ -2130,13 +2133,16 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TEUL;
mnemonic = "ld4u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TEQ;
mnemonic = "ld";
do_load:
- tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
- dc->mmuidx, memop);
+ if (!prefetch_nofault) {
+ tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
+ dc->mmuidx, memop);
+ }
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
reg_names[srcbdest], reg_names[srca]);
return TILEGX_EXCP_NONE;
--
1.9.3
[-- Attachment #2: 0001-target-tilegx-Implement-prefetch-instructions-in-pip.patch --]
[-- Type: application/octet-stream, Size: 2508 bytes --]
From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001
From: Chen Gang <gang.chen.5i5j@gmail.com>
Date: Tue, 20 Oct 2015 23:19:02 +0800
Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
Originally, tilegx qemu only implement prefetch instructions in pipe x1,
did not implement them in pipe y2.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
---
target-tilegx/translate.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 34d45f8..b8ca401 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2105,6 +2105,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
unsigned srcbdest = get_SrcBDest_Y2(bundle);
const char *mnemonic;
TCGMemOp memop;
+ bool prefetch_nofault = false;
switch (OEY2(opc, mode)) {
case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
@@ -2114,6 +2115,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_UB;
mnemonic = "ld1u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_TESW;
@@ -2122,6 +2124,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
memop = MO_TEUW;
mnemonic = "ld2u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TESL;
@@ -2130,13 +2133,16 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TEUL;
mnemonic = "ld4u";
+ prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
goto do_load;
case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
memop = MO_TEQ;
mnemonic = "ld";
do_load:
- tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
- dc->mmuidx, memop);
+ if (!prefetch_nofault) {
+ tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
+ dc->mmuidx, memop);
+ }
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
reg_names[srcbdest], reg_names[srca]);
return TILEGX_EXCP_NONE;
--
1.9.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
2015-10-20 15:26 [Qemu-devel] [PATCH] target-tilegx: Implement prefetch instructions in pipe y2 Chen Gang
@ 2015-10-22 17:53 ` Richard Henderson
[not found] ` <56295C28.8030300@hotmail.com>
0 siblings, 1 reply; 3+ messages in thread
From: Richard Henderson @ 2015-10-22 17:53 UTC (permalink / raw)
To: Chen Gang, Peter Maydell, Chris Metcalf; +Cc: qemu-devel
On 10/20/2015 05:26 AM, Chen Gang wrote:
>>From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001
> From: Chen Gang <gang.chen.5i5j@gmail.com>
> Date: Tue, 20 Oct 2015 23:19:02 +0800
> Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
>
> Originally, tilegx qemu only implement prefetch instructions in pipe x1,
> did not implement them in pipe y2.
>
> Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Applied.
r~
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
[not found] ` <56295C28.8030300@hotmail.com>
@ 2015-10-22 21:57 ` Chen Gang
0 siblings, 0 replies; 3+ messages in thread
From: Chen Gang @ 2015-10-22 21:57 UTC (permalink / raw)
To: rth@twiddle.net, Peter Maydell, Chris Metcalf; +Cc: qemu-devel
On 10/23/15 01:53, Richard Henderson wrote:
> On 10/20/2015 05:26 AM, Chen Gang wrote:
>>> From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001
>> From: Chen Gang <gang.chen.5i5j@gmail.com>
>> Date: Tue, 20 Oct 2015 23:19:02 +0800
>> Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
>>
>> Originally, tilegx qemu only implement prefetch instructions in pipe x1,
>> did not implement them in pipe y2.
>>
>> Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
>
> Applied.
>
OK, thanks. And at present, I am trying to implement floating point
insns within this month. Hope I can succeed.
Welcome any members' additional ideas, suggestions, and completions.
Thanks.
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-10-20 15:26 [Qemu-devel] [PATCH] target-tilegx: Implement prefetch instructions in pipe y2 Chen Gang
2015-10-22 17:53 ` Richard Henderson
[not found] ` <56295C28.8030300@hotmail.com>
2015-10-22 21:57 ` Chen Gang
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