From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54187) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zpfhw-0006Ai-Je for qemu-devel@nongnu.org; Fri, 23 Oct 2015 13:00:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zpfhs-0006F2-Hw for qemu-devel@nongnu.org; Fri, 23 Oct 2015 13:00:48 -0400 Received: from mx1.redhat.com ([209.132.183.28]:42261) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zpfhs-0006Ej-8b for qemu-devel@nongnu.org; Fri, 23 Oct 2015 13:00:44 -0400 References: <1445364840-7056-1-git-send-email-lersek@redhat.com> <20151021183625.26940.67906@jljusten-ivb> <5628A0E8.8050705@redhat.com> <20151022180407.GA9969@morn.lan> <56293D30.3080507@redhat.com> <20151023044115.30810.77352@jljusten-ivb> <5629E12E.4090409@redhat.com> <20151023165431.GA18431@morn.lan> From: Paolo Bonzini Message-ID: <562A67B6.1090804@redhat.com> Date: Fri, 23 Oct 2015 19:00:38 +0200 MIME-Version: 1.0 In-Reply-To: <20151023165431.GA18431@morn.lan> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] hw/isa/lpc_ich9: inject the SMI on the VCPU that is writing to APM_CNT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Kevin O'Connor Cc: "Michael S. Tsirkin" , Jordan Justen , qemu-devel@nongnu.org, Gerd Hoffmann , Michael Kinney , Laszlo Ersek On 23/10/2015 18:54, Kevin O'Connor wrote: >> > >> > Extra privileges compared to what? Legacy BIOS does not really put >> > anything privileged in SMRAM, while OVMF does and _hence_ relocates the >> > SMBASE of the AP. It would have been nice to get it right from the >> > beginning, but right now it's not worth forcing a lockstep QEMU-SeaBIOS >> > update. > We could add code to SeaBIOS now that protects against multiple SMI > handlers running, and then at some future date QEMU could be updated. > I'll defer to your judgment if that makes sense. > > BTW, how does OVMF handle SMIs on multiple processors? Does it setup > a unique SMBASE for each cpu, or does it inspect the apic id (or > something similar) in the smi handler to determine which cpu should > handle the event? It does the former. Paolo