* [Qemu-devel] [PATCH v1 1/6] target-*: Don't redefine cpu_exec()
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
@ 2015-10-26 15:27 ` Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 2/6] target-*: cpu.h: Undefine core code symbols Peter Crosthwaite
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Peter Crosthwaite @ 2015-10-26 15:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, pbonzini, Riku Voipio, Peter Crosthwaite
This function needs to be converted to a QOM hook and virtualised for
multi-arch. This rename interferes, as cpu-qom will not have access
to the renaming causing name divergence. This rename doesn't really do
anything anyway so just delete it.
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
Changed since RFCv3:
Add bsd-user changes
Add change to target-tilegx (new arch)
Fix reference to "cpu_arm_exec" in comment
bsd-user/main.c | 4 ++--
include/exec/cpu-all.h | 2 ++
linux-user/main.c | 32 ++++++++++++++++----------------
target-alpha/cpu.h | 2 --
target-arm/cpu.h | 2 --
target-cris/cpu.h | 2 --
target-i386/cpu.h | 2 --
target-lm32/cpu.h | 2 --
target-m68k/cpu.h | 2 --
target-microblaze/cpu.h | 2 --
target-mips/cpu.h | 2 --
target-moxie/cpu.h | 2 --
target-openrisc/cpu.h | 2 --
target-ppc/cpu.h | 2 --
target-s390x/cpu.h | 2 --
target-sh4/cpu.h | 2 --
target-sparc/cpu.h | 2 --
target-tilegx/cpu.h | 2 --
target-tricore/cpu.h | 2 --
target-unicore32/cpu.h | 1 -
target-xtensa/cpu.h | 2 --
21 files changed, 20 insertions(+), 53 deletions(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index adf2de0..ed116f5 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -171,7 +171,7 @@ void cpu_loop(CPUX86State *env)
//target_siginfo_t info;
for(;;) {
- trapnr = cpu_x86_exec(cs);
+ trapnr = cpu_exec(cs);
switch(trapnr) {
case 0x80:
/* syscall from int $0x80 */
@@ -512,7 +512,7 @@ void cpu_loop(CPUSPARCState *env)
//target_siginfo_t info;
while (1) {
- trapnr = cpu_sparc_exec(cs);
+ trapnr = cpu_exec(cs);
switch (trapnr) {
#ifndef TARGET_SPARC64
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index f9998b9..482d765 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -283,4 +283,6 @@ void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf);
int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
uint8_t *buf, int len, int is_write);
+int cpu_exec(CPUState *cpu);
+
#endif /* CPU_ALL_H */
diff --git a/linux-user/main.c b/linux-user/main.c
index 8acfe0f..877b865 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -145,7 +145,7 @@ static inline void exclusive_idle(void)
}
/* Start an exclusive operation.
- Must only be called from outside cpu_arm_exec. */
+ Must only be called from outside cpu_exec. */
static inline void start_exclusive(void)
{
CPUState *other_cpu;
@@ -278,7 +278,7 @@ void cpu_loop(CPUX86State *env)
for(;;) {
cpu_exec_start(cs);
- trapnr = cpu_x86_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch(trapnr) {
case 0x80:
@@ -672,7 +672,7 @@ void cpu_loop(CPUARMState *env)
for(;;) {
cpu_exec_start(cs);
- trapnr = cpu_arm_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch(trapnr) {
case EXCP_UDEF:
@@ -1003,7 +1003,7 @@ void cpu_loop(CPUARMState *env)
for (;;) {
cpu_exec_start(cs);
- trapnr = cpu_arm_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
@@ -1085,7 +1085,7 @@ void cpu_loop(CPUUniCore32State *env)
for (;;) {
cpu_exec_start(cs);
- trapnr = uc32_cpu_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
case UC32_EXCP_PRIV:
@@ -1286,7 +1286,7 @@ void cpu_loop (CPUSPARCState *env)
while (1) {
cpu_exec_start(cs);
- trapnr = cpu_sparc_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
/* Compute PSR before exposing state. */
@@ -1566,7 +1566,7 @@ void cpu_loop(CPUPPCState *env)
for(;;) {
cpu_exec_start(cs);
- trapnr = cpu_ppc_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch(trapnr) {
case POWERPC_EXCP_NONE:
@@ -2418,7 +2418,7 @@ void cpu_loop(CPUMIPSState *env)
for(;;) {
cpu_exec_start(cs);
- trapnr = cpu_mips_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch(trapnr) {
case EXCP_SYSCALL:
@@ -2655,7 +2655,7 @@ void cpu_loop(CPUOpenRISCState *env)
for (;;) {
cpu_exec_start(cs);
- trapnr = cpu_openrisc_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
gdbsig = 0;
@@ -2745,7 +2745,7 @@ void cpu_loop(CPUSH4State *env)
while (1) {
cpu_exec_start(cs);
- trapnr = cpu_sh4_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
@@ -2807,7 +2807,7 @@ void cpu_loop(CPUCRISState *env)
while (1) {
cpu_exec_start(cs);
- trapnr = cpu_cris_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
case 0xaa:
@@ -2868,7 +2868,7 @@ void cpu_loop(CPUMBState *env)
while (1) {
cpu_exec_start(cs);
- trapnr = cpu_mb_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
case 0xaa:
@@ -2973,7 +2973,7 @@ void cpu_loop(CPUM68KState *env)
for(;;) {
cpu_exec_start(cs);
- trapnr = cpu_m68k_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch(trapnr) {
case EXCP_ILLEGAL:
@@ -3112,7 +3112,7 @@ void cpu_loop(CPUAlphaState *env)
while (1) {
cpu_exec_start(cs);
- trapnr = cpu_alpha_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
/* All of the traps imply a transition through PALcode, which
@@ -3300,7 +3300,7 @@ void cpu_loop(CPUS390XState *env)
while (1) {
cpu_exec_start(cs);
- trapnr = cpu_s390x_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
case EXCP_INTERRUPT:
@@ -3604,7 +3604,7 @@ void cpu_loop(CPUTLGState *env)
while (1) {
cpu_exec_start(cs);
- trapnr = cpu_tilegx_exec(cs);
+ trapnr = cpu_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
case TILEGX_EXCP_SYSCALL:
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index bcd8076..d8e3737 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -286,7 +286,6 @@ struct CPUAlphaState {
};
#define cpu_list alpha_cpu_list
-#define cpu_exec cpu_alpha_exec
#define cpu_signal_handler cpu_alpha_signal_handler
#include "exec/cpu-all.h"
@@ -428,7 +427,6 @@ AlphaCPU *cpu_alpha_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_alpha_init(cpu_model))
void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
-int cpu_alpha_exec(CPUState *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3daa7f5..cc1265d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -509,7 +509,6 @@ typedef struct CPUARMState {
#include "cpu-qom.h"
ARMCPU *cpu_arm_init(const char *cpu_model);
-int cpu_arm_exec(CPUState *cpu);
target_ulong do_arm_semihosting(CPUARMState *env);
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
@@ -1607,7 +1606,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
-#define cpu_exec cpu_arm_exec
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 3220460..e6f6c9a 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -175,7 +175,6 @@ typedef struct CPUCRISState {
#include "cpu-qom.h"
CRISCPU *cpu_cris_init(const char *cpu_model);
-int cpu_cris_exec(CPUState *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -222,7 +221,6 @@ enum {
#define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model))
-#define cpu_exec cpu_cris_exec
#define cpu_signal_handler cpu_cris_signal_handler
/* MMU modes definitions */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 62f7879..0119d9e 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -994,7 +994,6 @@ typedef struct CPUX86State {
X86CPU *cpu_x86_init(const char *cpu_model);
X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
-int cpu_x86_exec(CPUState *cpu);
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
void x86_cpudef_setup(void);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
@@ -1164,7 +1163,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
-#define cpu_exec cpu_x86_exec
#define cpu_signal_handler cpu_x86_signal_handler
#define cpu_list x86_cpu_list
#define cpudef_setup x86_cpudef_setup
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 2b7620c..54eeb64 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -197,7 +197,6 @@ static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
#include "cpu-qom.h"
LM32CPU *cpu_lm32_init(const char *cpu_model);
-int cpu_lm32_exec(CPUState *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -218,7 +217,6 @@ bool lm32_cpu_do_semihosting(CPUState *cs);
#define cpu_init(cpu_model) CPU(cpu_lm32_init(cpu_model))
#define cpu_list lm32_cpu_list
-#define cpu_exec cpu_lm32_exec
#define cpu_signal_handler cpu_lm32_signal_handler
int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 224c169..186f37b 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -115,7 +115,6 @@ typedef struct CPUM68KState {
void m68k_tcg_init(void);
void m68k_cpu_init_gdb(M68kCPU *cpu);
M68kCPU *cpu_m68k_init(const char *cpu_model);
-int cpu_m68k_exec(CPUState *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -212,7 +211,6 @@ void register_m68k_insns (CPUM68KState *env);
#define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
-#define cpu_exec cpu_m68k_exec
#define cpu_signal_handler cpu_m68k_signal_handler
#define cpu_list m68k_cpu_list
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 6b212ab..2f47268 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -279,7 +279,6 @@ struct CPUMBState {
void mb_tcg_init(void);
MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
-int cpu_mb_exec(CPUState *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -294,7 +293,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
#define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
-#define cpu_exec cpu_mb_exec
#define cpu_signal_handler cpu_mb_signal_handler
/* MMU modes definitions */
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index f32a0fd..69d001e 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -619,7 +619,6 @@ void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
-#define cpu_exec cpu_mips_exec
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list
@@ -744,7 +743,6 @@ enum {
*/
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
-int cpu_mips_exec(CPUState *cpu);
void mips_tcg_init(void);
MIPSCPU *cpu_mips_init(const char *cpu_model);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index a612744..9fea329 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -110,7 +110,6 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState *env)
#define ENV_OFFSET offsetof(MoxieCPU, env)
MoxieCPU *cpu_moxie_init(const char *cpu_model);
-int cpu_moxie_exec(CPUState *cpu);
void moxie_cpu_do_interrupt(CPUState *cs);
void moxie_cpu_dump_state(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
@@ -121,7 +120,6 @@ int cpu_moxie_signal_handler(int host_signum, void *pinfo,
#define cpu_init(cpu_model) CPU(cpu_moxie_init(cpu_model))
-#define cpu_exec cpu_moxie_exec
#define cpu_signal_handler cpu_moxie_signal_handler
static inline int cpu_mmu_index(CPUMoxieState *env, bool ifetch)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index eb71607..8dbdbba 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -345,7 +345,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
-int cpu_openrisc_exec(CPUState *cpu);
void openrisc_cpu_do_interrupt(CPUState *cpu);
bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
@@ -359,7 +358,6 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_list cpu_openrisc_list
-#define cpu_exec cpu_openrisc_exec
#define cpu_signal_handler cpu_openrisc_signal_handler
#ifndef CONFIG_USER_ONLY
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index b34aed6..989bd78 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1165,7 +1165,6 @@ do { \
PowerPCCPU *cpu_ppc_init(const char *cpu_model);
void ppc_translate_init(void);
void gen_update_current_nip(void *opaque);
-int cpu_ppc_exec (CPUState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
is returned if the signal was handled by the virtual CPU. */
@@ -1241,7 +1240,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
-#define cpu_exec cpu_ppc_exec
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 658cd9d..89104ef 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -415,7 +415,6 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
S390CPU *cpu_s390x_init(const char *cpu_model);
void s390x_translate_init(void);
-int cpu_s390x_exec(CPUState *cpu);
/* you can call this signal handler from your SIGBUS and SIGSEGV
signal handlers to inform the virtual CPU of exceptions. non zero
@@ -597,7 +596,6 @@ bool css_present(uint8_t cssid);
#endif
#define cpu_init(model) CPU(cpu_s390x_init(model))
-#define cpu_exec cpu_s390x_exec
#define cpu_signal_handler cpu_s390x_signal_handler
void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 5b022c5..6c52729 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -192,7 +192,6 @@ typedef struct CPUSH4State {
void sh4_translate_init(void);
SuperHCPU *cpu_sh4_init(const char *cpu_model);
-int cpu_sh4_exec(CPUState *s);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
void *puc);
int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
@@ -225,7 +224,6 @@ void cpu_load_tlb(CPUSH4State * env);
#define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
-#define cpu_exec cpu_sh4_exec
#define cpu_signal_handler cpu_sh4_signal_handler
#define cpu_list sh4_cpu_list
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 9fa770b..cb10049 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -532,7 +532,6 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
void gen_intermediate_code_init(CPUSPARCState *env);
/* cpu-exec.c */
-int cpu_sparc_exec(CPUState *cpu);
/* win_helper.c */
target_ulong cpu_get_psr(CPUSPARCState *env1);
@@ -592,7 +591,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model))
#endif
-#define cpu_exec cpu_sparc_exec
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 03df107..23b4a61 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -159,14 +159,12 @@ static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
#include "exec/cpu-all.h"
void tilegx_tcg_init(void);
-int cpu_tilegx_exec(CPUState *s);
int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
TileGXCPU *cpu_tilegx_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
-#define cpu_exec cpu_tilegx_exec
#define cpu_signal_handler cpu_tilegx_signal_handler
static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
index 20a12f3..3a3fdb4 100644
--- a/target-tricore/cpu.h
+++ b/target-tricore/cpu.h
@@ -344,7 +344,6 @@ void psw_write(CPUTriCoreState *env, uint32_t val);
void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
-#define cpu_exec cpu_tricore_exec
#define cpu_signal_handler cpu_tricore_signal_handler
#define cpu_list tricore_cpu_list
@@ -370,7 +369,6 @@ enum {
};
void cpu_state_reset(CPUTriCoreState *s);
-int cpu_tricore_exec(CPUState *cpu);
void tricore_tcg_init(void);
int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 01c370c..ab3fc3d 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -120,7 +120,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
#define UC32_HWCAP_CMOV 4 /* 1 << 2 */
#define UC32_HWCAP_UCF64 8 /* 1 << 3 */
-#define cpu_exec uc32_cpu_exec
#define cpu_signal_handler uc32_cpu_signal_handler
int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 15ce010..36cbeba 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -382,7 +382,6 @@ typedef struct CPUXtensaState {
#include "cpu-qom.h"
-#define cpu_exec cpu_xtensa_exec
#define cpu_signal_handler cpu_xtensa_signal_handler
#define cpu_list xtensa_cpu_list
@@ -398,7 +397,6 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model);
void xtensa_translate_init(void);
void xtensa_breakpoint_handler(CPUState *cs);
-int cpu_xtensa_exec(CPUState *cpu);
void xtensa_finalize_config(XtensaConfig *config);
void xtensa_register_core(XtensaConfigList *node);
void check_interrupts(CPUXtensaState *s);
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH v1 2/6] target-*: cpu.h: Undefine core code symbols
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 1/6] target-*: Don't redefine cpu_exec() Peter Crosthwaite
@ 2015-10-26 15:27 ` Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 3/6] arm: cpu: static inline cpu_arm_init() Peter Crosthwaite
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Peter Crosthwaite @ 2015-10-26 15:27 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, Peter Crosthwaite
Pre-undefine all symbols that cpu.h defines for the sake of core code.
This is to allow inclusion of multiple cpu.h's from system level code
implementing multi-arch machines.
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
Such system level code cannot validly use these symbols as they are
ambiguous. So we should probably add some sort of poisoning system as
follow up work.
include/exec/cpu-defs-clear.h | 33 +++++++++++++++++++++++++++++++++
target-alpha/cpu.h | 1 +
target-arm/cpu.h | 1 +
target-cris/cpu.h | 1 +
target-i386/cpu.h | 1 +
target-lm32/cpu.h | 2 ++
target-m68k/cpu.h | 2 ++
target-microblaze/cpu.h | 1 +
target-mips/cpu.h | 2 ++
target-moxie/cpu.h | 1 +
target-openrisc/cpu.h | 2 ++
target-ppc/cpu.h | 1 +
target-s390x/cpu.h | 1 +
target-sh4/cpu.h | 1 +
target-sparc/cpu.h | 1 +
target-tilegx/cpu.h | 1 +
target-tricore/cpu.h | 1 +
target-unicore32/cpu.h | 2 ++
target-xtensa/cpu.h | 2 ++
19 files changed, 57 insertions(+)
create mode 100644 include/exec/cpu-defs-clear.h
diff --git a/include/exec/cpu-defs-clear.h b/include/exec/cpu-defs-clear.h
new file mode 100644
index 0000000..f801612
--- /dev/null
+++ b/include/exec/cpu-defs-clear.h
@@ -0,0 +1,33 @@
+/*
+ * Undefine the standard macros defined by cpu.h which are used by core code.
+ * Each arch cpu.h should include this before defining any of these symbols.
+ * This is to allow system level code to include multiple arches cpu.h.
+ *
+ * Copyright (c) 2015 Peter Crosthwaite <crosthwaite.peter@gmail.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* No multiple include guard intended. */
+
+#undef CPUArchState
+
+#undef ELF_MACHINE
+
+#undef TARGET_LONG_BITS
+#undef TARGET_PAGE_BITS
+#undef TARGET_PHYS_ADDR_SPACE_BITS
+#undef TARGET_VIRT_ADDR_SPACE_BITS
+
+#undef NB_MMU_MODES
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index d8e3737..bdd8be2 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -22,6 +22,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#define TARGET_LONG_BITS 64
#define ALIGNED_ONLY
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index cc1265d..4b702df 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -20,6 +20,7 @@
#define CPU_ARM_H
#include "config.h"
+#include "exec/cpu-defs-clear.h"
#include "kvm-consts.h"
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index e6f6c9a..bcd7e1a 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -22,6 +22,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#define TARGET_LONG_BITS 32
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 0119d9e..1623490 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -22,6 +22,7 @@
#include "config.h"
#include "qemu-common.h"
#include "standard-headers/asm-x86/hyperv.h"
+#include "exec/cpu-defs-clear.h"
#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 54eeb64..3b6e33e 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -20,6 +20,8 @@
#ifndef CPU_LM32_H
#define CPU_LM32_H
+#include "exec/cpu-defs-clear.h"
+
#define TARGET_LONG_BITS 32
#define CPUArchState struct CPULM32State
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 186f37b..800406e 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -20,6 +20,8 @@
#ifndef CPU_M68K_H
#define CPU_M68K_H
+#include "exec/cpu-defs-clear.h"
+
#define TARGET_LONG_BITS 32
#define CPUArchState struct CPUM68KState
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 2f47268..7532d9c 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -21,6 +21,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#define TARGET_LONG_BITS 32
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 69d001e..44497f7 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -5,6 +5,8 @@
#define ALIGNED_ONLY
+#include "exec/cpu-defs-clear.h"
+
#define CPUArchState struct CPUMIPSState
#include "config.h"
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index 9fea329..b3e23ad 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -21,6 +21,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#define TARGET_LONG_BITS 32
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 8dbdbba..70943bd 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -20,6 +20,8 @@
#ifndef CPU_OPENRISC_H
#define CPU_OPENRISC_H
+#include "exec/cpu-defs-clear.h"
+
#define TARGET_LONG_BITS 32
#define CPUArchState struct CPUOpenRISCState
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 989bd78..799b8d3 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -21,6 +21,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
//#define PPC_EMULATE_32BITS_HYPV
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 89104ef..46c038b 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -24,6 +24,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#define TARGET_LONG_BITS 64
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 6c52729..b45bb4e 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -21,6 +21,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#define TARGET_LONG_BITS 32
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index cb10049..82d993c 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -3,6 +3,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#include "qemu/bswap.h"
#define ALIGNED_ONLY
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 23b4a61..0134f30 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -21,6 +21,7 @@
#include "config.h"
#include "qemu-common.h"
+#include "exec/cpu-defs-clear.h"
#define TARGET_LONG_BITS 64
diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
index 3a3fdb4..1ce246c 100644
--- a/target-tricore/cpu.h
+++ b/target-tricore/cpu.h
@@ -19,6 +19,7 @@
#if !defined(__TRICORE_CPU_H__)
#define __TRICORE_CPU_H__
+#include "exec/cpu-defs-clear.h"
#include "tricore-defs.h"
#include "config.h"
#include "qemu-common.h"
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index ab3fc3d..db210c9 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -11,6 +11,8 @@
#ifndef QEMU_UNICORE32_CPU_H
#define QEMU_UNICORE32_CPU_H
+#include "exec/cpu-defs-clear.h"
+
#define TARGET_LONG_BITS 32
#define TARGET_PAGE_BITS 12
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 36cbeba..47ff99e 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -28,6 +28,8 @@
#ifndef CPU_XTENSA_H
#define CPU_XTENSA_H
+#include "exec/cpu-defs-clear.h"
+
#define ALIGNED_ONLY
#define TARGET_LONG_BITS 32
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH v1 3/6] arm: cpu: static inline cpu_arm_init()
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 1/6] target-*: Don't redefine cpu_exec() Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 2/6] target-*: cpu.h: Undefine core code symbols Peter Crosthwaite
@ 2015-10-26 15:27 ` Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 4/6] target-arm: Split cp helper API to new C file Peter Crosthwaite
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Peter Crosthwaite @ 2015-10-26 15:27 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, pbonzini, Peter Crosthwaite
Move this implementation up to the header so it is visible from system
level code once the architecture is converted to arch-obj-y. Alternative
would be to create init.c in target-arm/hw but this implementation is
trivial enough for static inline.
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
target-arm/cpu.h | 6 +++++-
target-arm/helper.c | 5 -----
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 4b702df..6b6485b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -509,7 +509,11 @@ typedef struct CPUARMState {
#include "cpu-qom.h"
-ARMCPU *cpu_arm_init(const char *cpu_model);
+static inline ARMCPU *cpu_arm_init(const char *cpu_model)
+{
+ return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
+}
+
target_ulong do_arm_semihosting(CPUARMState *env);
void aarch64_sync_32_to_64(CPUARMState *env);
void aarch64_sync_64_to_32(CPUARMState *env);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e7fda37..3118267 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4501,11 +4501,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
-ARMCPU *cpu_arm_init(const char *cpu_model)
-{
- return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
-}
-
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
{
CPUState *cs = CPU(cpu);
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH v1 4/6] target-arm: Split cp helper API to new C file
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
` (2 preceding siblings ...)
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 3/6] arm: cpu: static inline cpu_arm_init() Peter Crosthwaite
@ 2015-10-26 15:27 ` Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 5/6] hw: arm: Explicitly include cpu.h for consumers Peter Crosthwaite
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Peter Crosthwaite @ 2015-10-26 15:27 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, Peter Crosthwaite
Move the ARM coprocessor API to a new C file. helper.c is huge and
splitting off this self contained piece increases modularity.
This also prepares support for multi-arch where this file needs to
remain obj-y while the others in target-arm are converted to
arch-obj-y. This is because these are the only APIs in helper.c that
are directly callable from system level code.
Cc. Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
Changed since RFCv3:
Added below-the-line commentary to commit-message proper.
Fix incorrect include path for cpu.h (remove stray ../)
target-arm/Makefile.objs | 1 +
target-arm/cp.c | 328 +++++++++++++++++++++++++++++++++++++++++++++++
target-arm/helper.c | 324 ----------------------------------------------
3 files changed, 329 insertions(+), 324 deletions(-)
create mode 100644 target-arm/cp.c
diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs
index 9460b40..6d9f62e 100644
--- a/target-arm/Makefile.objs
+++ b/target-arm/Makefile.objs
@@ -5,6 +5,7 @@ obj-$(call land,$(CONFIG_KVM),$(call lnot,$(TARGET_AARCH64))) += kvm32.o
obj-$(call land,$(CONFIG_KVM),$(TARGET_AARCH64)) += kvm64.o
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
obj-y += translate.o op_helper.o helper.o cpu.o
+obj-y += cp.o
obj-y += neon_helper.o iwmmxt_helper.o
obj-y += gdbstub.o
obj-$(CONFIG_SOFTMMU) += psci.o
diff --git a/target-arm/cp.c b/target-arm/cp.c
new file mode 100644
index 0000000..541407f
--- /dev/null
+++ b/target-arm/cp.c
@@ -0,0 +1,328 @@
+#include "qemu-common.h"
+#include "cpu.h"
+
+static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
+{
+ /* Return true if the regdef would cause an assertion if you called
+ * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
+ * program bug for it not to have the NO_RAW flag).
+ * NB that returning false here doesn't necessarily mean that calling
+ * read/write_raw_cp_reg() is safe, because we can't distinguish "has
+ * read/write access functions which are safe for raw use" from "has
+ * read/write access functions which have side effects but has forgotten
+ * to provide raw access functions".
+ * The tests here line up with the conditions in read/write_raw_cp_reg()
+ * and assertions in raw_read()/raw_write().
+ */
+ if ((ri->type & ARM_CP_CONST) ||
+ ri->fieldoffset ||
+ ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
+ return false;
+ }
+ return true;
+}
+
+static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
+ void *opaque, int state, int secstate,
+ int crm, int opc1, int opc2)
+{
+ /* Private utility function for define_one_arm_cp_reg_with_opaque():
+ * add a single reginfo struct to the hash table.
+ */
+ uint32_t *key = g_new(uint32_t, 1);
+ ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
+ int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
+ int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+
+ /* Reset the secure state to the specific incoming state. This is
+ * necessary as the register may have been defined with both states.
+ */
+ r2->secure = secstate;
+
+ if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
+ /* Register is banked (using both entries in array).
+ * Overwriting fieldoffset as the array is only used to define
+ * banked registers but later only fieldoffset is used.
+ */
+ r2->fieldoffset = r->bank_fieldoffsets[ns];
+ }
+
+ if (state == ARM_CP_STATE_AA32) {
+ if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
+ /* If the register is banked then we don't need to migrate or
+ * reset the 32-bit instance in certain cases:
+ *
+ * 1) If the register has both 32-bit and 64-bit instances then we
+ * can count on the 64-bit instance taking care of the
+ * non-secure bank.
+ * 2) If ARMv8 is enabled then we can count on a 64-bit version
+ * taking care of the secure bank. This requires that separate
+ * 32 and 64-bit definitions are provided.
+ */
+ if ((r->state == ARM_CP_STATE_BOTH && ns) ||
+ (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
+ r2->type |= ARM_CP_ALIAS;
+ }
+ } else if ((secstate != r->secure) && !ns) {
+ /* The register is not banked so we only want to allow migration of
+ * the non-secure instance.
+ */
+ r2->type |= ARM_CP_ALIAS;
+ }
+
+ if (r->state == ARM_CP_STATE_BOTH) {
+ /* We assume it is a cp15 register if the .cp field is left unset.
+ */
+ if (r2->cp == 0) {
+ r2->cp = 15;
+ }
+
+#ifdef HOST_WORDS_BIGENDIAN
+ if (r2->fieldoffset) {
+ r2->fieldoffset += sizeof(uint32_t);
+ }
+#endif
+ }
+ }
+ if (state == ARM_CP_STATE_AA64) {
+ /* To allow abbreviation of ARMCPRegInfo
+ * definitions, we treat cp == 0 as equivalent to
+ * the value for "standard guest-visible sysreg".
+ * STATE_BOTH definitions are also always "standard
+ * sysreg" in their AArch64 view (the .cp value may
+ * be non-zero for the benefit of the AArch32 view).
+ */
+ if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
+ r2->cp = CP_REG_ARM64_SYSREG_CP;
+ }
+ *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
+ r2->opc0, opc1, opc2);
+ } else {
+ *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
+ }
+ if (opaque) {
+ r2->opaque = opaque;
+ }
+ /* reginfo passed to helpers is correct for the actual access,
+ * and is never ARM_CP_STATE_BOTH:
+ */
+ r2->state = state;
+ /* Make sure reginfo passed to helpers for wildcarded regs
+ * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
+ */
+ r2->crm = crm;
+ r2->opc1 = opc1;
+ r2->opc2 = opc2;
+ /* By convention, for wildcarded registers only the first
+ * entry is used for migration; the others are marked as
+ * ALIAS so we don't try to transfer the register
+ * multiple times. Special registers (ie NOP/WFI) are
+ * never migratable and not even raw-accessible.
+ */
+ if ((r->type & ARM_CP_SPECIAL)) {
+ r2->type |= ARM_CP_NO_RAW;
+ }
+ if (((r->crm == CP_ANY) && crm != 0) ||
+ ((r->opc1 == CP_ANY) && opc1 != 0) ||
+ ((r->opc2 == CP_ANY) && opc2 != 0)) {
+ r2->type |= ARM_CP_ALIAS;
+ }
+
+ /* Check that raw accesses are either forbidden or handled. Note that
+ * we can't assert this earlier because the setup of fieldoffset for
+ * banked registers has to be done first.
+ */
+ if (!(r2->type & ARM_CP_NO_RAW)) {
+ assert(!raw_accessors_invalid(r2));
+ }
+
+ /* Overriding of an existing definition must be explicitly
+ * requested.
+ */
+ if (!(r->type & ARM_CP_OVERRIDE)) {
+ ARMCPRegInfo *oldreg;
+ oldreg = g_hash_table_lookup(cpu->cp_regs, key);
+ if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
+ fprintf(stderr, "Register redefined: cp=%d %d bit "
+ "crn=%d crm=%d opc1=%d opc2=%d, "
+ "was %s, now %s\n", r2->cp, 32 + 32 * is64,
+ r2->crn, r2->crm, r2->opc1, r2->opc2,
+ oldreg->name, r2->name);
+ g_assert_not_reached();
+ }
+ }
+ g_hash_table_insert(cpu->cp_regs, key, r2);
+}
+
+
+void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
+ const ARMCPRegInfo *r, void *opaque)
+{
+ /* Define implementations of coprocessor registers.
+ * We store these in a hashtable because typically
+ * there are less than 150 registers in a space which
+ * is 16*16*16*8*8 = 262144 in size.
+ * Wildcarding is supported for the crm, opc1 and opc2 fields.
+ * If a register is defined twice then the second definition is
+ * used, so this can be used to define some generic registers and
+ * then override them with implementation specific variations.
+ * At least one of the original and the second definition should
+ * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
+ * against accidental use.
+ *
+ * The state field defines whether the register is to be
+ * visible in the AArch32 or AArch64 execution state. If the
+ * state is set to ARM_CP_STATE_BOTH then we synthesise a
+ * reginfo structure for the AArch32 view, which sees the lower
+ * 32 bits of the 64 bit register.
+ *
+ * Only registers visible in AArch64 may set r->opc0; opc0 cannot
+ * be wildcarded. AArch64 registers are always considered to be 64
+ * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
+ * the register, if any.
+ */
+ int crm, opc1, opc2, state;
+ int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
+ int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
+ int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
+ int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
+ int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
+ int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
+ /* 64 bit registers have only CRm and Opc1 fields */
+ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
+ /* op0 only exists in the AArch64 encodings */
+ assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
+ /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
+ assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
+ /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
+ * encodes a minimum access level for the register. We roll this
+ * runtime check into our general permission check code, so check
+ * here that the reginfo's specified permissions are strict enough
+ * to encompass the generic architectural permission check.
+ */
+ if (r->state != ARM_CP_STATE_AA32) {
+ int mask = 0;
+ switch (r->opc1) {
+ case 0: case 1: case 2:
+ /* min_EL EL1 */
+ mask = PL1_RW;
+ break;
+ case 3:
+ /* min_EL EL0 */
+ mask = PL0_RW;
+ break;
+ case 4:
+ /* min_EL EL2 */
+ mask = PL2_RW;
+ break;
+ case 5:
+ /* unallocated encoding, so not possible */
+ assert(false);
+ break;
+ case 6:
+ /* min_EL EL3 */
+ mask = PL3_RW;
+ break;
+ case 7:
+ /* min_EL EL1, secure mode only (we don't check the latter) */
+ mask = PL1_RW;
+ break;
+ default:
+ /* broken reginfo with out-of-range opc1 */
+ assert(false);
+ break;
+ }
+ /* assert our permissions are not too lax (stricter is fine) */
+ assert((r->access & ~mask) == 0);
+ }
+
+ /* Check that the register definition has enough info to handle
+ * reads and writes if they are permitted.
+ */
+ if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
+ if (r->access & PL3_R) {
+ assert((r->fieldoffset ||
+ (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
+ r->readfn);
+ }
+ if (r->access & PL3_W) {
+ assert((r->fieldoffset ||
+ (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
+ r->writefn);
+ }
+ }
+ /* Bad type field probably means missing sentinel at end of reg list */
+ assert(cptype_valid(r->type));
+ for (crm = crmmin; crm <= crmmax; crm++) {
+ for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
+ for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
+ for (state = ARM_CP_STATE_AA32;
+ state <= ARM_CP_STATE_AA64; state++) {
+ if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
+ continue;
+ }
+ if (state == ARM_CP_STATE_AA32) {
+ /* Under AArch32 CP registers can be common
+ * (same for secure and non-secure world) or banked.
+ */
+ switch (r->secure) {
+ case ARM_CP_SECSTATE_S:
+ case ARM_CP_SECSTATE_NS:
+ add_cpreg_to_hashtable(cpu, r, opaque, state,
+ r->secure, crm, opc1, opc2);
+ break;
+ default:
+ add_cpreg_to_hashtable(cpu, r, opaque, state,
+ ARM_CP_SECSTATE_S,
+ crm, opc1, opc2);
+ add_cpreg_to_hashtable(cpu, r, opaque, state,
+ ARM_CP_SECSTATE_NS,
+ crm, opc1, opc2);
+ break;
+ }
+ } else {
+ /* AArch64 registers get mapped to non-secure instance
+ * of AArch32 */
+ add_cpreg_to_hashtable(cpu, r, opaque, state,
+ ARM_CP_SECSTATE_NS,
+ crm, opc1, opc2);
+ }
+ }
+ }
+ }
+ }
+}
+
+void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
+ const ARMCPRegInfo *regs, void *opaque)
+{
+ /* Define a whole list of registers */
+ const ARMCPRegInfo *r;
+ for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
+ define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
+ }
+}
+
+const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
+{
+ return g_hash_table_lookup(cpregs, &encoded_cp);
+}
+
+void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Helper coprocessor write function for write-ignore registers */
+}
+
+uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ /* Helper coprocessor write function for read-as-zero registers */
+ return 0;
+}
+
+void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
+{
+ /* Helper coprocessor reset function for do-nothing-on-reset registers */
+}
+
+
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3118267..80e2b2a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -179,27 +179,6 @@ static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
}
}
-static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
-{
- /* Return true if the regdef would cause an assertion if you called
- * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
- * program bug for it not to have the NO_RAW flag).
- * NB that returning false here doesn't necessarily mean that calling
- * read/write_raw_cp_reg() is safe, because we can't distinguish "has
- * read/write access functions which are safe for raw use" from "has
- * read/write access functions which have side effects but has forgotten
- * to provide raw access functions".
- * The tests here line up with the conditions in read/write_raw_cp_reg()
- * and assertions in raw_read()/raw_write().
- */
- if ((ri->type & ARM_CP_CONST) ||
- ri->fieldoffset ||
- ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
- return false;
- }
- return true;
-}
-
bool write_cpustate_to_list(ARMCPU *cpu)
{
/* Write the coprocessor state from cpu->env to the (index,value) list. */
@@ -4606,309 +4585,6 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
return cpu_list;
}
-static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- void *opaque, int state, int secstate,
- int crm, int opc1, int opc2)
-{
- /* Private utility function for define_one_arm_cp_reg_with_opaque():
- * add a single reginfo struct to the hash table.
- */
- uint32_t *key = g_new(uint32_t, 1);
- ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
- int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
- int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
-
- /* Reset the secure state to the specific incoming state. This is
- * necessary as the register may have been defined with both states.
- */
- r2->secure = secstate;
-
- if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
- /* Register is banked (using both entries in array).
- * Overwriting fieldoffset as the array is only used to define
- * banked registers but later only fieldoffset is used.
- */
- r2->fieldoffset = r->bank_fieldoffsets[ns];
- }
-
- if (state == ARM_CP_STATE_AA32) {
- if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
- /* If the register is banked then we don't need to migrate or
- * reset the 32-bit instance in certain cases:
- *
- * 1) If the register has both 32-bit and 64-bit instances then we
- * can count on the 64-bit instance taking care of the
- * non-secure bank.
- * 2) If ARMv8 is enabled then we can count on a 64-bit version
- * taking care of the secure bank. This requires that separate
- * 32 and 64-bit definitions are provided.
- */
- if ((r->state == ARM_CP_STATE_BOTH && ns) ||
- (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
- r2->type |= ARM_CP_ALIAS;
- }
- } else if ((secstate != r->secure) && !ns) {
- /* The register is not banked so we only want to allow migration of
- * the non-secure instance.
- */
- r2->type |= ARM_CP_ALIAS;
- }
-
- if (r->state == ARM_CP_STATE_BOTH) {
- /* We assume it is a cp15 register if the .cp field is left unset.
- */
- if (r2->cp == 0) {
- r2->cp = 15;
- }
-
-#ifdef HOST_WORDS_BIGENDIAN
- if (r2->fieldoffset) {
- r2->fieldoffset += sizeof(uint32_t);
- }
-#endif
- }
- }
- if (state == ARM_CP_STATE_AA64) {
- /* To allow abbreviation of ARMCPRegInfo
- * definitions, we treat cp == 0 as equivalent to
- * the value for "standard guest-visible sysreg".
- * STATE_BOTH definitions are also always "standard
- * sysreg" in their AArch64 view (the .cp value may
- * be non-zero for the benefit of the AArch32 view).
- */
- if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
- r2->cp = CP_REG_ARM64_SYSREG_CP;
- }
- *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
- r2->opc0, opc1, opc2);
- } else {
- *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
- }
- if (opaque) {
- r2->opaque = opaque;
- }
- /* reginfo passed to helpers is correct for the actual access,
- * and is never ARM_CP_STATE_BOTH:
- */
- r2->state = state;
- /* Make sure reginfo passed to helpers for wildcarded regs
- * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
- */
- r2->crm = crm;
- r2->opc1 = opc1;
- r2->opc2 = opc2;
- /* By convention, for wildcarded registers only the first
- * entry is used for migration; the others are marked as
- * ALIAS so we don't try to transfer the register
- * multiple times. Special registers (ie NOP/WFI) are
- * never migratable and not even raw-accessible.
- */
- if ((r->type & ARM_CP_SPECIAL)) {
- r2->type |= ARM_CP_NO_RAW;
- }
- if (((r->crm == CP_ANY) && crm != 0) ||
- ((r->opc1 == CP_ANY) && opc1 != 0) ||
- ((r->opc2 == CP_ANY) && opc2 != 0)) {
- r2->type |= ARM_CP_ALIAS;
- }
-
- /* Check that raw accesses are either forbidden or handled. Note that
- * we can't assert this earlier because the setup of fieldoffset for
- * banked registers has to be done first.
- */
- if (!(r2->type & ARM_CP_NO_RAW)) {
- assert(!raw_accessors_invalid(r2));
- }
-
- /* Overriding of an existing definition must be explicitly
- * requested.
- */
- if (!(r->type & ARM_CP_OVERRIDE)) {
- ARMCPRegInfo *oldreg;
- oldreg = g_hash_table_lookup(cpu->cp_regs, key);
- if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
- fprintf(stderr, "Register redefined: cp=%d %d bit "
- "crn=%d crm=%d opc1=%d opc2=%d, "
- "was %s, now %s\n", r2->cp, 32 + 32 * is64,
- r2->crn, r2->crm, r2->opc1, r2->opc2,
- oldreg->name, r2->name);
- g_assert_not_reached();
- }
- }
- g_hash_table_insert(cpu->cp_regs, key, r2);
-}
-
-
-void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
- const ARMCPRegInfo *r, void *opaque)
-{
- /* Define implementations of coprocessor registers.
- * We store these in a hashtable because typically
- * there are less than 150 registers in a space which
- * is 16*16*16*8*8 = 262144 in size.
- * Wildcarding is supported for the crm, opc1 and opc2 fields.
- * If a register is defined twice then the second definition is
- * used, so this can be used to define some generic registers and
- * then override them with implementation specific variations.
- * At least one of the original and the second definition should
- * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
- * against accidental use.
- *
- * The state field defines whether the register is to be
- * visible in the AArch32 or AArch64 execution state. If the
- * state is set to ARM_CP_STATE_BOTH then we synthesise a
- * reginfo structure for the AArch32 view, which sees the lower
- * 32 bits of the 64 bit register.
- *
- * Only registers visible in AArch64 may set r->opc0; opc0 cannot
- * be wildcarded. AArch64 registers are always considered to be 64
- * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
- * the register, if any.
- */
- int crm, opc1, opc2, state;
- int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
- int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
- int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
- int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
- int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
- int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
- /* 64 bit registers have only CRm and Opc1 fields */
- assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
- /* op0 only exists in the AArch64 encodings */
- assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
- /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
- assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
- /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
- * encodes a minimum access level for the register. We roll this
- * runtime check into our general permission check code, so check
- * here that the reginfo's specified permissions are strict enough
- * to encompass the generic architectural permission check.
- */
- if (r->state != ARM_CP_STATE_AA32) {
- int mask = 0;
- switch (r->opc1) {
- case 0: case 1: case 2:
- /* min_EL EL1 */
- mask = PL1_RW;
- break;
- case 3:
- /* min_EL EL0 */
- mask = PL0_RW;
- break;
- case 4:
- /* min_EL EL2 */
- mask = PL2_RW;
- break;
- case 5:
- /* unallocated encoding, so not possible */
- assert(false);
- break;
- case 6:
- /* min_EL EL3 */
- mask = PL3_RW;
- break;
- case 7:
- /* min_EL EL1, secure mode only (we don't check the latter) */
- mask = PL1_RW;
- break;
- default:
- /* broken reginfo with out-of-range opc1 */
- assert(false);
- break;
- }
- /* assert our permissions are not too lax (stricter is fine) */
- assert((r->access & ~mask) == 0);
- }
-
- /* Check that the register definition has enough info to handle
- * reads and writes if they are permitted.
- */
- if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
- if (r->access & PL3_R) {
- assert((r->fieldoffset ||
- (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
- r->readfn);
- }
- if (r->access & PL3_W) {
- assert((r->fieldoffset ||
- (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
- r->writefn);
- }
- }
- /* Bad type field probably means missing sentinel at end of reg list */
- assert(cptype_valid(r->type));
- for (crm = crmmin; crm <= crmmax; crm++) {
- for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
- for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
- for (state = ARM_CP_STATE_AA32;
- state <= ARM_CP_STATE_AA64; state++) {
- if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
- continue;
- }
- if (state == ARM_CP_STATE_AA32) {
- /* Under AArch32 CP registers can be common
- * (same for secure and non-secure world) or banked.
- */
- switch (r->secure) {
- case ARM_CP_SECSTATE_S:
- case ARM_CP_SECSTATE_NS:
- add_cpreg_to_hashtable(cpu, r, opaque, state,
- r->secure, crm, opc1, opc2);
- break;
- default:
- add_cpreg_to_hashtable(cpu, r, opaque, state,
- ARM_CP_SECSTATE_S,
- crm, opc1, opc2);
- add_cpreg_to_hashtable(cpu, r, opaque, state,
- ARM_CP_SECSTATE_NS,
- crm, opc1, opc2);
- break;
- }
- } else {
- /* AArch64 registers get mapped to non-secure instance
- * of AArch32 */
- add_cpreg_to_hashtable(cpu, r, opaque, state,
- ARM_CP_SECSTATE_NS,
- crm, opc1, opc2);
- }
- }
- }
- }
- }
-}
-
-void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
- const ARMCPRegInfo *regs, void *opaque)
-{
- /* Define a whole list of registers */
- const ARMCPRegInfo *r;
- for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
- define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
- }
-}
-
-const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
-{
- return g_hash_table_lookup(cpregs, &encoded_cp);
-}
-
-void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
-{
- /* Helper coprocessor write function for write-ignore registers */
-}
-
-uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
-{
- /* Helper coprocessor write function for read-as-zero registers */
- return 0;
-}
-
-void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
-{
- /* Helper coprocessor reset function for do-nothing-on-reset registers */
-}
-
static int bad_mode_switch(CPUARMState *env, int mode)
{
/* Return true if it is not valid for us to switch to
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH v1 5/6] hw: arm: Explicitly include cpu.h for consumers
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
` (3 preceding siblings ...)
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 4/6] target-arm: Split cp helper API to new C file Peter Crosthwaite
@ 2015-10-26 15:27 ` Peter Crosthwaite
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 6/6] hw: mb: boot " Peter Crosthwaite
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Peter Crosthwaite @ 2015-10-26 15:27 UTC (permalink / raw)
To: qemu-devel; +Cc: pbonzini, Peter Crosthwaite, Peter Crosthwaite, Peter Maydell
From: Peter Crosthwaite <crosthwaitepeter@gmail.com>
Device land code that needs cpu.h only needs it for architecture
specific reasons. So include target-arm/cpu.h explicitly rather than
the one provided by common code.
This prepares support for multi-arch where the common cpu.h will be
minimal and not contain any arch specifics.
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
hw/arm/strongarm.h | 2 ++
include/hw/arm/arm.h | 3 +++
include/hw/arm/digic.h | 2 ++
include/hw/arm/exynos4210.h | 2 ++
include/hw/arm/omap.h | 2 ++
include/hw/arm/pxa.h | 2 ++
6 files changed, 13 insertions(+)
diff --git a/hw/arm/strongarm.h b/hw/arm/strongarm.h
index 2893f94..6f5d163 100644
--- a/hw/arm/strongarm.h
+++ b/hw/arm/strongarm.h
@@ -3,6 +3,8 @@
#include "exec/memory.h"
+#include "target-arm/cpu.h"
+
#define SA_CS0 0x00000000
#define SA_CS1 0x08000000
#define SA_CS2 0x10000000
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index 4dcd4f9..cddb38d 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -11,6 +11,9 @@
#ifndef ARM_MISC_H
#define ARM_MISC_H 1
+#include "qemu-common.h"
+#include "target-arm/cpu.h"
+
#include "exec/memory.h"
#include "hw/irq.h"
#include "qemu/notify.h"
diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h
index a739d6a..9f4bd52 100644
--- a/include/hw/arm/digic.h
+++ b/include/hw/arm/digic.h
@@ -23,6 +23,8 @@
#include "hw/timer/digic-timer.h"
#include "hw/char/digic-uart.h"
+#include "target-arm/cpu.h"
+
#define TYPE_DIGIC "digic"
#define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC)
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index 5c1820f..3fb9684 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -29,6 +29,8 @@
#include "qemu-common.h"
#include "exec/memory.h"
+#include "target-arm/cpu.h"
+
#define EXYNOS4210_NCPUS 2
#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index 0ad5fb8..7e0d0e4 100644
--- a/include/hw/arm/omap.h
+++ b/include/hw/arm/omap.h
@@ -21,6 +21,8 @@
# define hw_omap_h "omap.h"
#include "hw/irq.h"
+#include "target-arm/cpu.h"
+
# define OMAP_EMIFS_BASE 0x00000000
# define OMAP2_Q0_BASE 0x00000000
# define OMAP_CS0_BASE 0x00000000
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index 259b852..4d2f1f3 100644
--- a/include/hw/arm/pxa.h
+++ b/include/hw/arm/pxa.h
@@ -11,6 +11,8 @@
#include "exec/memory.h"
+#include "target-arm/cpu.h"
+
/* Interrupt numbers */
# define PXA2XX_PIC_SSP3 0
# define PXA2XX_PIC_USBH2 2
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Qemu-devel] [PATCH v1 6/6] hw: mb: boot Explicitly include cpu.h for consumers
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
` (4 preceding siblings ...)
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 5/6] hw: arm: Explicitly include cpu.h for consumers Peter Crosthwaite
@ 2015-10-26 15:27 ` Peter Crosthwaite
2015-10-26 15:34 ` [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Paolo Bonzini
2015-10-26 16:01 ` Peter Maydell
7 siblings, 0 replies; 10+ messages in thread
From: Peter Crosthwaite @ 2015-10-26 15:27 UTC (permalink / raw)
To: qemu-devel
Cc: pbonzini, Peter Crosthwaite, Peter Crosthwaite, Edgar E. Iglesias
From: Peter Crosthwaite <crosthwaitepeter@gmail.com>
boot.c only needs cpu.h for architecture specific reasons. So include
target-microblaze/cpu.h explicitly rather than the one provided by
common code.
This prepares support for multi-arch where the common cpu.h will be
minimal and not contain any arch specifics.
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
---
Changed since RFCv3:
Made commit message specific to boot.c
hw/microblaze/boot.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/microblaze/boot.h b/hw/microblaze/boot.h
index 0eb7f8e..a4d7740 100644
--- a/hw/microblaze/boot.h
+++ b/hw/microblaze/boot.h
@@ -3,6 +3,8 @@
#include "hw/hw.h"
+#include "target-microblaze/cpu.h"
+
void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
uint32_t ramsize,
const char *initrd_filename,
--
1.9.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
` (5 preceding siblings ...)
2015-10-26 15:27 ` [Qemu-devel] [PATCH v1 6/6] hw: mb: boot " Peter Crosthwaite
@ 2015-10-26 15:34 ` Paolo Bonzini
2015-10-26 16:01 ` Peter Maydell
7 siblings, 0 replies; 10+ messages in thread
From: Paolo Bonzini @ 2015-10-26 15:34 UTC (permalink / raw)
To: Peter Crosthwaite, qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite
On 26/10/2015 16:27, Peter Crosthwaite wrote:
> This is the second set of patches needed to enable Multi-arch system
> emulation. For full context refer to RFCv3:
>
> [PATCH v3 00/35] Multi Architecture System Emulation
> https://lists.gnu.org/archive/html/qemu-devel/2015-07/msg03929.html
>
> Phase 1 was mostly merged:
>
> [PATCH v1 00/15] Multi-Arch Phase 1
> https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03054.html
>
> This pack contains no functional diff, but contains some of the higher
> diff refactorings that prepare MA support. It makes a start on the
> arch-specific changes needed touching Microblaze and ARM and giving an
> idea of what an Arches hw/<arch> and target-<arch> are going to look
> like after conversion.
>
> Original cover, as well as overall series state below for further
> information.
>
> Regards,
> Peter
>
> Original Multi-arch arch patch series cover:
>
> ***
>
> This is target-multi, a system-mode build that can support multiple
> cpu-types.
>
> Two architectures are initially converted. Microblaze and ARM. Step
> by step conversion in done for each. A microblaze is added to
> Xilinx Zynq platform as a test case. This will be elaborted more in
> future spins. This use case is valid, as Microblazes can be added (any
> number of them!) in Zynq FPGA programmable logic configuration.
>
> The general approach (radically different to approach in V1 RFC) is to build
> and prelink an object (arch-obj.o) per-arch containing:
>
> 1: target-foo/*
> 2: All uses of env internals and CPU_GET_ENV
> * cputlb, translate-all, cpu-exec
> * TCG backend
>
> This means cputlb and friends are compiled multiple times fo each arch. The
> symbols for each of these pre-links are then localised to avoid link time name
> collisions. This is based on Paolo's suggestion to templatify cputlb and
> friends. Just the net of what to multi-compile is widened to include the TCG
> stuff as well now.
>
> Despite being some "major surgery" this approach actually solves many of big
> the problems raised in V1. Big problems sovled:
>
> 1: With the multi-compile TCG backends there are now multiple tcg_ctx's for
> each architecture. This solves the issue PMM raised WRT false positives on TB
> hashing as archs no longer share translation context.
>
> 2: There is no longer a need to reorder the CPU_COMMON within the ENV or the ENV
> within the CPU. This was flagged as a performance issue by multiple people in
> V1.
> All users of the env internals as well as ENV_GET_CPU are now in multi-compile
> code and so multi-arch does not need to define a generic ENV nor does in need to
> def the problematic ENV_GET_CPU.
>
> 3: With the prelink symbol localisation, link time namespace collision of
> helpers from multiple arches is no longer an issue. No need to bloat all the
> function names with arch specific prefixes.
>
> 4: The architecture specifics used/defined by cpu-defs can now vary from arch to
> arch (incl. target_ulong) greatly reducing coversion effort needed. The list
> of restrictions for multi-arch capability is much reduced since V1. No
> target_long issues anymore.
>
> include/exec/*.h and some of the common code needs some refactoring to setup
> this single vs multi compile split. Mostly code movements.
>
> Some functions (like tcg_enabled) need to be listified for each of the
> now-multiple TCG engines.
>
> The interface between the multi compile and single compiled files needs to be
> virtualised using QOM cpu functions. But this is now a very low footprint
> change as most of the virtualised hooks are now in mutli-compiled code (they
> only exist as text once). There are more new hooks than before, but the per
> target change pattern is reduced.
>
> For the implementation of the series, the trickiest part is (still) cpu.h
> inclusion management. There are now more than one cpu.h's and different
> parts of the tree need a different include scheme. target-multi defines
> it's own cpu.h which is bare minimum defs as needed by core code only.
> target-foo/cpu.h are mostly the same but refactored to avoid collisions
> with other cpu.h's. Inclusion scheme goes something like
> this (for the multi-arch build):
>
> *: Core code includes only target-multi/cpu.h
> *: target-foo/ implementation code includes target-foo/cpu.h locally
> *: System level code (e.g. mach models) can use multiple target-foo/cpu.h's
>
> The hardest unasnwered Q is (still) what to do about bootloading. Currently
> each arch has it's own architecture specific bootloading which may assume a
> single architecture. I have applied some hacks to at least get this
> RFC testable using a -kernel -firmware split but going forward being
> able to associate an elf/image with a cpu explictitly needs to be
> solved.
>
> No support for KVM, im not sure if a mix of TCG and KVM is supported even for
> a single arch? (which would be prerequisite to MA KVM).
>
> ***
>
> Current review state of full multi-arch work in progress branch:
>
> target-*: Don't redefine cpu_exec()
> target-*: cpu.h: Undefine core code symbols
> arm: cpu: static inline cpu_arm_init()
> target-arm: Split cp helper API to new C file
> hw: arm: Explicitly include cpu.h for consumers
> hw: mb: Explicitly include cpu.h for consumers
> translate: Listify tcg_exec_init() R:rth@twiddle.net
> cpus: Listify cpu_list() function
> translate-common: Listify tcg_enabled()
> core: Convert tcg_enabled() uses to any/all variants
> exec-all: Move cpu_can_do_io() to qom/cpu.h R:rth@twiddle.net
> cpu-common: Define tb_page_addr_t for everyone
> include/exec: Split target_long def to new header
> cpu-defs: Allow multiple inclusions
> Makefile.target: Introduce arch-obj
> core: virtualise CPU interfaces completely
> core: Introduce multi-arch build
> arm: register cpu_list() function
> arm: enable multi-arch
> microblaze: enable multi-arch
> arm: boot: Don't assume all CPUs are ARM
> arm: xilinx_zynq: Add a Microblaze
> HACK: mb: boot: Assume using -firmware for mb software
> HACK: mb: boot: Disable dtb load in multi-arch
>
>
> Peter Crosthwaite (6):
> target-*: Don't redefine cpu_exec()
> target-*: cpu.h: Undefine core code symbols
> arm: cpu: static inline cpu_arm_init()
> target-arm: Split cp helper API to new C file
> hw: arm: Explicitly include cpu.h for consumers
> hw: mb: boot Explicitly include cpu.h for consumers
>
> bsd-user/main.c | 4 +-
> hw/arm/strongarm.h | 2 +
> hw/microblaze/boot.h | 2 +
> include/exec/cpu-all.h | 2 +
> include/exec/cpu-defs-clear.h | 33 +++++
> include/hw/arm/arm.h | 3 +
> include/hw/arm/digic.h | 2 +
> include/hw/arm/exynos4210.h | 2 +
> include/hw/arm/omap.h | 2 +
> include/hw/arm/pxa.h | 2 +
> linux-user/main.c | 32 ++--
> target-alpha/cpu.h | 3 +-
> target-arm/Makefile.objs | 1 +
> target-arm/cp.c | 328 +++++++++++++++++++++++++++++++++++++++++
> target-arm/cpu.h | 9 +-
> target-arm/helper.c | 329 ------------------------------------------
> target-cris/cpu.h | 3 +-
> target-i386/cpu.h | 3 +-
> target-lm32/cpu.h | 4 +-
> target-m68k/cpu.h | 4 +-
> target-microblaze/cpu.h | 3 +-
> target-mips/cpu.h | 4 +-
> target-moxie/cpu.h | 3 +-
> target-openrisc/cpu.h | 4 +-
> target-ppc/cpu.h | 3 +-
> target-s390x/cpu.h | 3 +-
> target-sh4/cpu.h | 3 +-
> target-sparc/cpu.h | 3 +-
> target-tilegx/cpu.h | 3 +-
> target-tricore/cpu.h | 3 +-
> target-unicore32/cpu.h | 3 +-
> target-xtensa/cpu.h | 4 +-
> 32 files changed, 426 insertions(+), 383 deletions(-)
> create mode 100644 include/exec/cpu-defs-clear.h
> create mode 100644 target-arm/cp.c
>
I think we can merge all patches except 2 in 2.5, but it depends on
Peter as they would go through his tree (only patch 1 is generic,
everything else is ARM). They definitely were posted before soft freeze.
Paolo
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2
2015-10-26 15:27 [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Peter Crosthwaite
` (6 preceding siblings ...)
2015-10-26 15:34 ` [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2 Paolo Bonzini
@ 2015-10-26 16:01 ` Peter Maydell
2015-10-26 16:43 ` Peter Crosthwaite
7 siblings, 1 reply; 10+ messages in thread
From: Peter Maydell @ 2015-10-26 16:01 UTC (permalink / raw)
To: Peter Crosthwaite; +Cc: Paolo Bonzini, QEMU Developers, Peter Crosthwaite
On 26 October 2015 at 15:27, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> This is the second set of patches needed to enable Multi-arch system
> emulation. For full context refer to RFCv3:
>
> [PATCH v3 00/35] Multi Architecture System Emulation
> https://lists.gnu.org/archive/html/qemu-devel/2015-07/msg03929.html
>
> Phase 1 was mostly merged:
>
> [PATCH v1 00/15] Multi-Arch Phase 1
> https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03054.html
>
> This pack contains no functional diff, but contains some of the higher
> diff refactorings that prepare MA support. It makes a start on the
> arch-specific changes needed touching Microblaze and ARM and giving an
> idea of what an Arches hw/<arch> and target-<arch> are going to look
> like after conversion.
4/6 seems to overlap at least in spirit with the pulling out of
the cp API functions into their own header that Pavel has put
a patch out for...
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [Qemu-devel] [PATCH v1 0/6] Multi-Arch Phase 2
2015-10-26 16:01 ` Peter Maydell
@ 2015-10-26 16:43 ` Peter Crosthwaite
0 siblings, 0 replies; 10+ messages in thread
From: Peter Crosthwaite @ 2015-10-26 16:43 UTC (permalink / raw)
To: Peter Maydell, Pavel Fedin
Cc: Paolo Bonzini, QEMU Developers, Peter Crosthwaite
On Mon, Oct 26, 2015 at 9:01 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 26 October 2015 at 15:27, Peter Crosthwaite
> <crosthwaitepeter@gmail.com> wrote:
>> This is the second set of patches needed to enable Multi-arch system
>> emulation. For full context refer to RFCv3:
>>
>> [PATCH v3 00/35] Multi Architecture System Emulation
>> https://lists.gnu.org/archive/html/qemu-devel/2015-07/msg03929.html
>>
>> Phase 1 was mostly merged:
>>
>> [PATCH v1 00/15] Multi-Arch Phase 1
>> https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg03054.html
>>
>> This pack contains no functional diff, but contains some of the higher
>> diff refactorings that prepare MA support. It makes a start on the
>> arch-specific changes needed touching Microblaze and ARM and giving an
>> idea of what an Arches hw/<arch> and target-<arch> are going to look
>> like after conversion.
>
> 4/6 seems to overlap at least in spirit with the pulling out of
> the cp API functions into their own header that Pavel has put
> a patch out for...
>
Actually it looks related but conflict free. I am splitting off the
c-file implementation while he is going after the header. We can do
both, as our patches don't help each-others problem and there is no
one-shot solution that I can see. I have commented Pavels patch, as I
think we could shortcut that by just obj-y'ing GIC. Otherwise i'll
look into merging his and my patch into one series.
Regards,
Peter
> -- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread