From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 14/20] target/arm: Implement security attribute lookups for memory accesses
Date: Thu, 5 Oct 2017 14:39:33 -0400 [thread overview]
Message-ID: <562a5db1-ab3b-1d77-eb8e-69af276bcac3@linaro.org> (raw)
In-Reply-To: <1506092407-26985-15-git-send-email-peter.maydell@linaro.org>
On 09/22/2017 11:00 AM, Peter Maydell wrote:
> Implement the security attribute lookups for memory accesses
> in the get_phys_addr() functions, causing these to generate
> various kinds of SecureFault for bad accesses.
>
> The major subtlety in this code relates to handling of the
> case when the security attributes the SAU assigns to the
> address don't match the current security state of the CPU.
>
> In the ARM ARM pseudocode for validating instruction
> accesses, the security attributes of the address determine
> whether the Secure or NonSecure MPU state is used. At face
> value, handling this would require us to encode the relevant
> bits of state into mmu_idx for both S and NS at once, which
> would result in our needing 16 mmu indexes. Fortunately we
> don't actually need to do this because a mismatch between
> address attributes and CPU state means either:
> * some kind of fault (usually a SecureFault, but in theory
> perhaps a UserFault for unaligned access to Device memory)
> * execution of the SG instruction in NS state from a
> Secure & NonSecure code region
>
> The purpose of SG is simply to flip the CPU into Secure
> state, so we can handle it by emulating execution of that
> instruction directly in arm_v7m_cpu_do_interrupt(), which
> means we can treat all the mismatch cases as "throw an
> exception" and we don't need to encode the state of the
> other MPU bank into our mmu_idx values.
>
> This commit doesn't include the actual emulation of SG;
> it also doesn't include implementation of the IDAU, which
> is a per-board way to specify hard-coded memory attributes
> for addresses, which override the CPU-internal SAU if they
> specify a more secure setting than the SAU is programmed to.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/internals.h | 15 ++++
> target/arm/helper.c | 182 ++++++++++++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 195 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2017-10-05 18:39 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-22 14:59 [Qemu-devel] [PATCH 00/20] ARM v8M: exception entry, exit and security Peter Maydell
2017-09-22 14:59 ` [Qemu-devel] [PATCH 01/20] nvic: Clear the vector arrays and prigroup on reset Peter Maydell
2017-09-23 0:34 ` Richard Henderson
2017-09-29 21:03 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-09-22 14:59 ` [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target stack early in v7M exception return Peter Maydell
2017-10-05 4:44 ` Philippe Mathieu-Daudé
2017-10-05 16:04 ` Richard Henderson
2017-10-05 16:20 ` Peter Maydell
2017-10-06 13:22 ` Peter Maydell
2017-10-06 13:24 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 03/20] target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode Peter Maydell
2017-10-05 3:25 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:09 ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 04/20] target/arm: Restore security state on exception return Peter Maydell
2017-10-05 16:14 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 05/20] target/arm: Restore SPSEL to correct CONTROL register " Peter Maydell
2017-10-05 16:18 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M Peter Maydell
2017-10-05 16:25 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 07/20] target/arm: Warn about restoring to unaligned stack Peter Maydell
2017-09-29 21:05 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 16:28 ` [Qemu-devel] " Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 08/20] target/arm: Don't warn about exception return with PC low bit set for v8M Peter Maydell
2017-09-29 21:07 ` Philippe Mathieu-Daudé
2017-10-05 16:32 ` Richard Henderson
2017-10-05 16:34 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 09/20] target/arm: Add new-in-v8M SFSR and SFAR Peter Maydell
2017-10-05 16:39 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 10/20] target/arm: Update excret sanity checks for v8M Peter Maydell
2017-10-05 17:16 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 11/20] target/arm: Add support for restoring v8M additional state context Peter Maydell
2017-10-05 17:30 ` Richard Henderson
2017-09-22 14:59 ` [Qemu-devel] [PATCH 12/20] target/arm: Add v8M support to exception entry code Peter Maydell
2017-10-05 18:31 ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution Unit registers Peter Maydell
2017-10-05 18:33 ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 14/20] target/arm: Implement security attribute lookups for memory accesses Peter Maydell
2017-10-05 18:39 ` Richard Henderson [this message]
2017-09-22 15:00 ` [Qemu-devel] [PATCH 15/20] target/arm: Fix calculation of secure mm_idx values Peter Maydell
2017-10-05 4:46 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:41 ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 16/20] target/arm: Factor out "get mmuidx for specified security state" Peter Maydell
2017-10-05 3:29 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:42 ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction Peter Maydell
2017-09-22 17:18 ` [Qemu-devel] [Qemu-arm] " Peter Maydell
2017-10-05 18:50 ` [Qemu-devel] " Richard Henderson
2017-10-05 18:55 ` Peter Maydell
2017-10-05 18:57 ` Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 18/20] target/arm: Implement BLXNS Peter Maydell
2017-10-05 13:07 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 18:56 ` [Qemu-devel] " Richard Henderson
2017-10-05 19:40 ` Peter Maydell
2017-09-22 15:00 ` [Qemu-devel] [PATCH 19/20] target/arm: Implement secure function return Peter Maydell
2017-10-05 13:11 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:00 ` [Qemu-devel] " Richard Henderson
2017-09-22 15:00 ` [Qemu-devel] [PATCH 20/20] nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bit Peter Maydell
2017-10-05 4:33 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-10-05 19:01 ` [Qemu-devel] " Richard Henderson
2017-10-05 4:51 ` [Qemu-devel] [Qemu-arm] [PATCH 00/20] ARM v8M: exception entry, exit and security Philippe Mathieu-Daudé
2017-10-06 13:29 ` Peter Maydell
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