[Qemu-devel] [PATCH v3 0/5] Connect the SPI devices to ZynqMP

[Qemu-devel] [PATCH v3 0/5] Connect the SPI devices to ZynqMP

[Alistair Francis]

Connect the SPI devices to Xilinx's ZynqMP.

I also need to make some changes to the actual SPI device to
imporove the fuctionality, but for the time being this works.

V3:
 - Don't reach into the SoC to get the SPI Bus
V2:
 - Connect the SPI flash in the board code
 - Update git patches to properly indicate rename
 - Add sst25wf080 as a SPI flash


Alistair Francis (5):
  m25p80.c: Add sst25wf080 SPI flash device
  ssi: Move ssi.h into a separate directory
  xilinx_spips: Seperate the state struct into a header
  xlnx-zynqmp: Connect the SPI devices
  xlnx-ep108: Connect the SPI Flash

 hw/arm/pxa2xx.c                     |  2 +-
 hw/arm/spitz.c                      |  2 +-
 hw/arm/stellaris.c                  |  2 +-
 hw/arm/strongarm.c                  |  2 +-
 hw/arm/tosa.c                       |  2 +-
 hw/arm/xilinx_zynq.c                |  2 +-
 hw/arm/xlnx-ep108.c                 | 19 ++++++++++
 hw/arm/xlnx-zynqmp.c                | 37 +++++++++++++++++++
 hw/arm/z2.c                         |  2 +-
 hw/block/m25p80.c                   |  3 +-
 hw/display/ads7846.c                |  2 +-
 hw/display/ssd0323.c                |  2 +-
 hw/microblaze/petalogix_ml605_mmu.c |  2 +-
 hw/misc/max111x.c                   |  2 +-
 hw/sd/ssi-sd.c                      |  2 +-
 hw/ssi/pl022.c                      |  2 +-
 hw/ssi/ssi.c                        |  2 +-
 hw/ssi/xilinx_spi.c                 |  2 +-
 hw/ssi/xilinx_spips.c               | 56 ++++------------------------
 include/hw/arm/xlnx-zynqmp.h        |  4 ++
 include/hw/{ => ssi}/ssi.h          | 10 +++--
 include/hw/ssi/xilinx_spips.h       | 74 +++++++++++++++++++++++++++++++++++++
 22 files changed, 165 insertions(+), 68 deletions(-)
 rename include/hw/{ => ssi}/ssi.h (96%)
 create mode 100644 include/hw/ssi/xilinx_spips.h

-- 
2.5.0

[Qemu-devel] [PATCH v3 1/5] m25p80.c: Add sst25wf080 SPI flash device

[Alistair Francis]

Add the sst25wf080 SPI flash device.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---

 hw/block/m25p80.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index efc43dd..7b9f97c 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -163,6 +163,7 @@ static const FlashPartInfo known_devices[] = {
     { INFO("sst25wf010",  0xbf2502,      0,  64 << 10,   2, ER_4K) },
     { INFO("sst25wf020",  0xbf2503,      0,  64 << 10,   4, ER_4K) },
     { INFO("sst25wf040",  0xbf2504,      0,  64 << 10,   8, ER_4K) },
+    { INFO("sst25wf080",  0xbf2505,      0,  64 << 10,  16, ER_4K) },
 
     /* ST Microelectronics -- newer production may have feature updates */
     { INFO("m25p05",      0x202010,      0,  32 << 10,   2, 0) },
-- 
2.5.0

Re: [Qemu-devel] [PATCH v3 1/5] m25p80.c: Add sst25wf080 SPI flash device

[Peter Crosthwaite]

[-- Attachment #1: Type: text/plain, Size: 996 bytes --]

On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
alistair.francis@xilinx.com> wrote:

> Add the sst25wf080 SPI flash device.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>

Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>


> ---
>
>  hw/block/m25p80.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index efc43dd..7b9f97c 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -163,6 +163,7 @@ static const FlashPartInfo known_devices[] = {
>      { INFO("sst25wf010",  0xbf2502,      0,  64 << 10,   2, ER_4K) },
>      { INFO("sst25wf020",  0xbf2503,      0,  64 << 10,   4, ER_4K) },
>      { INFO("sst25wf040",  0xbf2504,      0,  64 << 10,   8, ER_4K) },
> +    { INFO("sst25wf080",  0xbf2505,      0,  64 << 10,  16, ER_4K) },
>
>      /* ST Microelectronics -- newer production may have feature updates */
>      { INFO("m25p05",      0x202010,      0,  32 << 10,   2, 0) },
> --
> 2.5.0
>
>

[-- Attachment #2: Type: text/html, Size: 1818 bytes --]

[Qemu-devel] [PATCH v3 2/5] ssi: Move ssi.h into a separate directory

[Alistair Francis]

Move the ssi.h include file into the ssi directory.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
 - Change git patch to indicate rename

 hw/arm/pxa2xx.c                     |  2 +-
 hw/arm/spitz.c                      |  2 +-
 hw/arm/stellaris.c                  |  2 +-
 hw/arm/strongarm.c                  |  2 +-
 hw/arm/tosa.c                       |  2 +-
 hw/arm/xilinx_zynq.c                |  2 +-
 hw/arm/z2.c                         |  2 +-
 hw/block/m25p80.c                   |  2 +-
 hw/display/ads7846.c                |  2 +-
 hw/display/ssd0323.c                |  2 +-
 hw/microblaze/petalogix_ml605_mmu.c |  2 +-
 hw/misc/max111x.c                   |  2 +-
 hw/sd/ssi-sd.c                      |  2 +-
 hw/ssi/pl022.c                      |  2 +-
 hw/ssi/ssi.c                        |  2 +-
 hw/ssi/xilinx_spi.c                 |  2 +-
 hw/ssi/xilinx_spips.c               |  2 +-
 include/hw/{ => ssi}/ssi.h          | 10 ++++++----
 18 files changed, 23 insertions(+), 21 deletions(-)
 rename include/hw/{ => ssi}/ssi.h (96%)

diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index 79d22d9..54bf152 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -12,7 +12,7 @@
 #include "sysemu/sysemu.h"
 #include "hw/char/serial.h"
 #include "hw/i2c/i2c.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "sysemu/char.h"
 #include "sysemu/block-backend.h"
 #include "sysemu/blockdev.h"
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index 8d3cc0b..ee8f889 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -16,7 +16,7 @@
 #include "sysemu/sysemu.h"
 #include "hw/pcmcia.h"
 #include "hw/i2c/i2c.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "hw/block/flash.h"
 #include "qemu/timer.h"
 #include "hw/devices.h"
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 3d6486f..c785e90 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -8,7 +8,7 @@
  */
 
 #include "hw/sysbus.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "hw/arm/arm.h"
 #include "hw/devices.h"
 #include "qemu/timer.h"
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index 9624ecb..4d2ba02 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -34,7 +34,7 @@
 #include "hw/arm/arm.h"
 #include "sysemu/char.h"
 #include "sysemu/sysemu.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 
 //#define DEBUG
 
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 02814d7..68ad01e 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -19,7 +19,7 @@
 #include "hw/pcmcia.h"
 #include "hw/boards.h"
 #include "hw/i2c/i2c.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "sysemu/block-backend.h"
 #include "hw/sysbus.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 9f89483..9db9602 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -24,7 +24,7 @@
 #include "hw/block/flash.h"
 #include "sysemu/block-backend.h"
 #include "hw/loader.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "qemu/error-report.h"
 
 #define NUM_SPI_FLASHES 4
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index b44eb76..c82fe2c 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -16,7 +16,7 @@
 #include "hw/arm/arm.h"
 #include "hw/devices.h"
 #include "hw/i2c/i2c.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "hw/boards.h"
 #include "sysemu/sysemu.h"
 #include "hw/block/flash.h"
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 7b9f97c..addd907 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -24,7 +24,7 @@
 #include "hw/hw.h"
 #include "sysemu/block-backend.h"
 #include "sysemu/blockdev.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 
 #ifndef M25P80_ERR_DEBUG
 #define M25P80_ERR_DEBUG 0
diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
index 3f35369..cb82317 100644
--- a/hw/display/ads7846.c
+++ b/hw/display/ads7846.c
@@ -10,7 +10,7 @@
  * GNU GPL, version 2 or (at your option) any later version.
  */
 
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "ui/console.h"
 
 typedef struct {
diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
index 9727007..7545da8 100644
--- a/hw/display/ssd0323.c
+++ b/hw/display/ssd0323.c
@@ -10,7 +10,7 @@
 /* The controller can support a variety of different displays, but we only
    implement one.  Most of the commends relating to brightness and geometry
    setup are ignored. */
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "ui/console.h"
 
 //#define DEBUG_SSD0323 1
diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c
index 462060f..5366cec 100644
--- a/hw/microblaze/petalogix_ml605_mmu.c
+++ b/hw/microblaze/petalogix_ml605_mmu.c
@@ -35,7 +35,7 @@
 #include "sysemu/block-backend.h"
 #include "hw/char/serial.h"
 #include "exec/address-spaces.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 
 #include "boot.h"
 
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
index bef3651..d619d61 100644
--- a/hw/misc/max111x.c
+++ b/hw/misc/max111x.c
@@ -10,7 +10,7 @@
  * GNU GPL, version 2 or (at your option) any later version.
  */
 
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 
 typedef struct {
     SSISlave parent_obj;
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index e4b2d4f..4fe00fd 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -12,7 +12,7 @@
 
 #include "sysemu/block-backend.h"
 #include "sysemu/blockdev.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "hw/sd.h"
 
 //#define DEBUG_SSI_SD 1
diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c
index 61d568f..0bbf633 100644
--- a/hw/ssi/pl022.c
+++ b/hw/ssi/pl022.c
@@ -8,7 +8,7 @@
  */
 
 #include "hw/sysbus.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 
 //#define DEBUG_PL022 1
 
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index 2aab79b..a0f57c0 100644
--- a/hw/ssi/ssi.c
+++ b/hw/ssi/ssi.c
@@ -12,7 +12,7 @@
  * GNU GPL, version 2 or (at your option) any later version.
  */
 
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 
 struct SSIBus {
     BusState parent_obj;
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
index 620573c..94bb2a7 100644
--- a/hw/ssi/xilinx_spi.c
+++ b/hw/ssi/xilinx_spi.c
@@ -29,7 +29,7 @@
 #include "qemu/log.h"
 #include "qemu/fifo8.h"
 
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 
 #ifdef XILINX_SPI_ERR_DEBUG
 #define DB_PRINT(...) do { \
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 0910f54..e9471ff 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -27,7 +27,7 @@
 #include "hw/ptimer.h"
 #include "qemu/log.h"
 #include "qemu/fifo8.h"
-#include "hw/ssi.h"
+#include "hw/ssi/ssi.h"
 #include "qemu/bitops.h"
 
 #ifndef XILINX_SPIPS_ERR_DEBUG
diff --git a/include/hw/ssi.h b/include/hw/ssi/ssi.h
similarity index 96%
rename from include/hw/ssi.h
rename to include/hw/ssi/ssi.h
index df0f838..4a0a539 100644
--- a/include/hw/ssi.h
+++ b/include/hw/ssi/ssi.h
@@ -14,6 +14,8 @@
 #include "hw/qdev.h"
 
 typedef struct SSISlave SSISlave;
+typedef struct SSISlaveClass SSISlaveClass;
+typedef enum SSICSMode SSICSMode;
 
 #define TYPE_SSI_SLAVE "ssi-slave"
 #define SSI_SLAVE(obj) \
@@ -25,14 +27,14 @@ typedef struct SSISlave SSISlave;
 
 #define SSI_GPIO_CS "ssi-gpio-cs"
 
-typedef enum {
+enum SSICSMode {
     SSI_CS_NONE = 0,
     SSI_CS_LOW,
     SSI_CS_HIGH,
-} SSICSMode;
+};
 
 /* Slave devices.  */
-typedef struct SSISlaveClass {
+struct SSISlaveClass {
     DeviceClass parent_class;
 
     int (*init)(SSISlave *dev);
@@ -55,7 +57,7 @@ typedef struct SSISlaveClass {
      * always be called for the device for every txrx access to the parent bus
      */
     uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val);
-} SSISlaveClass;
+};
 
 struct SSISlave {
     DeviceState parent_obj;
-- 
2.5.0

Re: [Qemu-devel] [PATCH v3 2/5] ssi: Move ssi.h into a separate directory

[Peter Crosthwaite]

[-- Attachment #1: Type: text/plain, Size: 8565 bytes --]

On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
alistair.francis@xilinx.com> wrote:

> Move the ssi.h include file into the ssi directory.
>
>
Needs a note about the typedef changes. You can drop those changes if you
want, as checkpatch is not an issue when moving code.


> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>

Either way:

Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>

Regards,
Peter

---
> V2:
>  - Change git patch to indicate rename
>
>  hw/arm/pxa2xx.c                     |  2 +-
>  hw/arm/spitz.c                      |  2 +-
>  hw/arm/stellaris.c                  |  2 +-
>  hw/arm/strongarm.c                  |  2 +-
>  hw/arm/tosa.c                       |  2 +-
>  hw/arm/xilinx_zynq.c                |  2 +-
>  hw/arm/z2.c                         |  2 +-
>  hw/block/m25p80.c                   |  2 +-
>  hw/display/ads7846.c                |  2 +-
>  hw/display/ssd0323.c                |  2 +-
>  hw/microblaze/petalogix_ml605_mmu.c |  2 +-
>  hw/misc/max111x.c                   |  2 +-
>  hw/sd/ssi-sd.c                      |  2 +-
>  hw/ssi/pl022.c                      |  2 +-
>  hw/ssi/ssi.c                        |  2 +-
>  hw/ssi/xilinx_spi.c                 |  2 +-
>  hw/ssi/xilinx_spips.c               |  2 +-
>  include/hw/{ => ssi}/ssi.h          | 10 ++++++----
>  18 files changed, 23 insertions(+), 21 deletions(-)
>  rename include/hw/{ => ssi}/ssi.h (96%)
>
> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
> index 79d22d9..54bf152 100644
> --- a/hw/arm/pxa2xx.c
> +++ b/hw/arm/pxa2xx.c
> @@ -12,7 +12,7 @@
>  #include "sysemu/sysemu.h"
>  #include "hw/char/serial.h"
>  #include "hw/i2c/i2c.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "sysemu/char.h"
>  #include "sysemu/block-backend.h"
>  #include "sysemu/blockdev.h"
> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
> index 8d3cc0b..ee8f889 100644
> --- a/hw/arm/spitz.c
> +++ b/hw/arm/spitz.c
> @@ -16,7 +16,7 @@
>  #include "sysemu/sysemu.h"
>  #include "hw/pcmcia.h"
>  #include "hw/i2c/i2c.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "hw/block/flash.h"
>  #include "qemu/timer.h"
>  #include "hw/devices.h"
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 3d6486f..c785e90 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -8,7 +8,7 @@
>   */
>
>  #include "hw/sysbus.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "hw/arm/arm.h"
>  #include "hw/devices.h"
>  #include "qemu/timer.h"
> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
> index 9624ecb..4d2ba02 100644
> --- a/hw/arm/strongarm.c
> +++ b/hw/arm/strongarm.c
> @@ -34,7 +34,7 @@
>  #include "hw/arm/arm.h"
>  #include "sysemu/char.h"
>  #include "sysemu/sysemu.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>
>  //#define DEBUG
>
> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
> index 02814d7..68ad01e 100644
> --- a/hw/arm/tosa.c
> +++ b/hw/arm/tosa.c
> @@ -19,7 +19,7 @@
>  #include "hw/pcmcia.h"
>  #include "hw/boards.h"
>  #include "hw/i2c/i2c.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "sysemu/block-backend.h"
>  #include "hw/sysbus.h"
>  #include "exec/address-spaces.h"
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 9f89483..9db9602 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -24,7 +24,7 @@
>  #include "hw/block/flash.h"
>  #include "sysemu/block-backend.h"
>  #include "hw/loader.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "qemu/error-report.h"
>
>  #define NUM_SPI_FLASHES 4
> diff --git a/hw/arm/z2.c b/hw/arm/z2.c
> index b44eb76..c82fe2c 100644
> --- a/hw/arm/z2.c
> +++ b/hw/arm/z2.c
> @@ -16,7 +16,7 @@
>  #include "hw/arm/arm.h"
>  #include "hw/devices.h"
>  #include "hw/i2c/i2c.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "hw/boards.h"
>  #include "sysemu/sysemu.h"
>  #include "hw/block/flash.h"
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 7b9f97c..addd907 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -24,7 +24,7 @@
>  #include "hw/hw.h"
>  #include "sysemu/block-backend.h"
>  #include "sysemu/blockdev.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>
>  #ifndef M25P80_ERR_DEBUG
>  #define M25P80_ERR_DEBUG 0
> diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
> index 3f35369..cb82317 100644
> --- a/hw/display/ads7846.c
> +++ b/hw/display/ads7846.c
> @@ -10,7 +10,7 @@
>   * GNU GPL, version 2 or (at your option) any later version.
>   */
>
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "ui/console.h"
>
>  typedef struct {
> diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
> index 9727007..7545da8 100644
> --- a/hw/display/ssd0323.c
> +++ b/hw/display/ssd0323.c
> @@ -10,7 +10,7 @@
>  /* The controller can support a variety of different displays, but we only
>     implement one.  Most of the commends relating to brightness and
> geometry
>     setup are ignored. */
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "ui/console.h"
>
>  //#define DEBUG_SSD0323 1
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c
> b/hw/microblaze/petalogix_ml605_mmu.c
> index 462060f..5366cec 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -35,7 +35,7 @@
>  #include "sysemu/block-backend.h"
>  #include "hw/char/serial.h"
>  #include "exec/address-spaces.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>
>  #include "boot.h"
>
> diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
> index bef3651..d619d61 100644
> --- a/hw/misc/max111x.c
> +++ b/hw/misc/max111x.c
> @@ -10,7 +10,7 @@
>   * GNU GPL, version 2 or (at your option) any later version.
>   */
>
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>
>  typedef struct {
>      SSISlave parent_obj;
> diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
> index e4b2d4f..4fe00fd 100644
> --- a/hw/sd/ssi-sd.c
> +++ b/hw/sd/ssi-sd.c
> @@ -12,7 +12,7 @@
>
>  #include "sysemu/block-backend.h"
>  #include "sysemu/blockdev.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "hw/sd.h"
>
>  //#define DEBUG_SSI_SD 1
> diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c
> index 61d568f..0bbf633 100644
> --- a/hw/ssi/pl022.c
> +++ b/hw/ssi/pl022.c
> @@ -8,7 +8,7 @@
>   */
>
>  #include "hw/sysbus.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>
>  //#define DEBUG_PL022 1
>
> diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
> index 2aab79b..a0f57c0 100644
> --- a/hw/ssi/ssi.c
> +++ b/hw/ssi/ssi.c
> @@ -12,7 +12,7 @@
>   * GNU GPL, version 2 or (at your option) any later version.
>   */
>
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>
>  struct SSIBus {
>      BusState parent_obj;
> diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
> index 620573c..94bb2a7 100644
> --- a/hw/ssi/xilinx_spi.c
> +++ b/hw/ssi/xilinx_spi.c
> @@ -29,7 +29,7 @@
>  #include "qemu/log.h"
>  #include "qemu/fifo8.h"
>
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>
>  #ifdef XILINX_SPI_ERR_DEBUG
>  #define DB_PRINT(...) do { \
> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
> index 0910f54..e9471ff 100644
> --- a/hw/ssi/xilinx_spips.c
> +++ b/hw/ssi/xilinx_spips.c
> @@ -27,7 +27,7 @@
>  #include "hw/ptimer.h"
>  #include "qemu/log.h"
>  #include "qemu/fifo8.h"
> -#include "hw/ssi.h"
> +#include "hw/ssi/ssi.h"
>  #include "qemu/bitops.h"
>
>  #ifndef XILINX_SPIPS_ERR_DEBUG
> diff --git a/include/hw/ssi.h b/include/hw/ssi/ssi.h
> similarity index 96%
> rename from include/hw/ssi.h
> rename to include/hw/ssi/ssi.h
> index df0f838..4a0a539 100644
> --- a/include/hw/ssi.h
> +++ b/include/hw/ssi/ssi.h
> @@ -14,6 +14,8 @@
>  #include "hw/qdev.h"
>
>  typedef struct SSISlave SSISlave;
> +typedef struct SSISlaveClass SSISlaveClass;
> +typedef enum SSICSMode SSICSMode;
>
>  #define TYPE_SSI_SLAVE "ssi-slave"
>  #define SSI_SLAVE(obj) \
> @@ -25,14 +27,14 @@ typedef struct SSISlave SSISlave;
>
>  #define SSI_GPIO_CS "ssi-gpio-cs"
>
> -typedef enum {
> +enum SSICSMode {
>      SSI_CS_NONE = 0,
>      SSI_CS_LOW,
>      SSI_CS_HIGH,
> -} SSICSMode;
> +};
>
>  /* Slave devices.  */
> -typedef struct SSISlaveClass {
> +struct SSISlaveClass {
>      DeviceClass parent_class;
>
>      int (*init)(SSISlave *dev);
> @@ -55,7 +57,7 @@ typedef struct SSISlaveClass {
>       * always be called for the device for every txrx access to the
> parent bus
>       */
>      uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val);
> -} SSISlaveClass;
> +};
>
>  struct SSISlave {
>      DeviceState parent_obj;
> --
> 2.5.0
>
>

[-- Attachment #2: Type: text/html, Size: 11612 bytes --]

Re: [Qemu-devel] [PATCH v3 2/5] ssi: Move ssi.h into a separate directory

[Alistair Francis]

On Wed, Oct 28, 2015 at 6:44 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
>
>
> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>>
>> Move the ssi.h include file into the ssi directory.
>>
>
> Needs a note about the typedef changes. You can drop those changes if you
> want, as checkpatch is not an issue when moving code.

Good point, I added a comment saying that I made some changes to pass
checkpatch.

>
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>
>
> Either way:
>
> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>

Thanks

Alistair

>
> Regards,
> Peter
>
>> ---
>> V2:
>>  - Change git patch to indicate rename
>>
>>  hw/arm/pxa2xx.c                     |  2 +-
>>  hw/arm/spitz.c                      |  2 +-
>>  hw/arm/stellaris.c                  |  2 +-
>>  hw/arm/strongarm.c                  |  2 +-
>>  hw/arm/tosa.c                       |  2 +-
>>  hw/arm/xilinx_zynq.c                |  2 +-
>>  hw/arm/z2.c                         |  2 +-
>>  hw/block/m25p80.c                   |  2 +-
>>  hw/display/ads7846.c                |  2 +-
>>  hw/display/ssd0323.c                |  2 +-
>>  hw/microblaze/petalogix_ml605_mmu.c |  2 +-
>>  hw/misc/max111x.c                   |  2 +-
>>  hw/sd/ssi-sd.c                      |  2 +-
>>  hw/ssi/pl022.c                      |  2 +-
>>  hw/ssi/ssi.c                        |  2 +-
>>  hw/ssi/xilinx_spi.c                 |  2 +-
>>  hw/ssi/xilinx_spips.c               |  2 +-
>>  include/hw/{ => ssi}/ssi.h          | 10 ++++++----
>>  18 files changed, 23 insertions(+), 21 deletions(-)
>>  rename include/hw/{ => ssi}/ssi.h (96%)
>>
>> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
>> index 79d22d9..54bf152 100644
>> --- a/hw/arm/pxa2xx.c
>> +++ b/hw/arm/pxa2xx.c
>> @@ -12,7 +12,7 @@
>>  #include "sysemu/sysemu.h"
>>  #include "hw/char/serial.h"
>>  #include "hw/i2c/i2c.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "sysemu/char.h"
>>  #include "sysemu/block-backend.h"
>>  #include "sysemu/blockdev.h"
>> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
>> index 8d3cc0b..ee8f889 100644
>> --- a/hw/arm/spitz.c
>> +++ b/hw/arm/spitz.c
>> @@ -16,7 +16,7 @@
>>  #include "sysemu/sysemu.h"
>>  #include "hw/pcmcia.h"
>>  #include "hw/i2c/i2c.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "hw/block/flash.h"
>>  #include "qemu/timer.h"
>>  #include "hw/devices.h"
>> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
>> index 3d6486f..c785e90 100644
>> --- a/hw/arm/stellaris.c
>> +++ b/hw/arm/stellaris.c
>> @@ -8,7 +8,7 @@
>>   */
>>
>>  #include "hw/sysbus.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "hw/arm/arm.h"
>>  #include "hw/devices.h"
>>  #include "qemu/timer.h"
>> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
>> index 9624ecb..4d2ba02 100644
>> --- a/hw/arm/strongarm.c
>> +++ b/hw/arm/strongarm.c
>> @@ -34,7 +34,7 @@
>>  #include "hw/arm/arm.h"
>>  #include "sysemu/char.h"
>>  #include "sysemu/sysemu.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>
>>  //#define DEBUG
>>
>> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
>> index 02814d7..68ad01e 100644
>> --- a/hw/arm/tosa.c
>> +++ b/hw/arm/tosa.c
>> @@ -19,7 +19,7 @@
>>  #include "hw/pcmcia.h"
>>  #include "hw/boards.h"
>>  #include "hw/i2c/i2c.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "sysemu/block-backend.h"
>>  #include "hw/sysbus.h"
>>  #include "exec/address-spaces.h"
>> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
>> index 9f89483..9db9602 100644
>> --- a/hw/arm/xilinx_zynq.c
>> +++ b/hw/arm/xilinx_zynq.c
>> @@ -24,7 +24,7 @@
>>  #include "hw/block/flash.h"
>>  #include "sysemu/block-backend.h"
>>  #include "hw/loader.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "qemu/error-report.h"
>>
>>  #define NUM_SPI_FLASHES 4
>> diff --git a/hw/arm/z2.c b/hw/arm/z2.c
>> index b44eb76..c82fe2c 100644
>> --- a/hw/arm/z2.c
>> +++ b/hw/arm/z2.c
>> @@ -16,7 +16,7 @@
>>  #include "hw/arm/arm.h"
>>  #include "hw/devices.h"
>>  #include "hw/i2c/i2c.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "hw/boards.h"
>>  #include "sysemu/sysemu.h"
>>  #include "hw/block/flash.h"
>> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
>> index 7b9f97c..addd907 100644
>> --- a/hw/block/m25p80.c
>> +++ b/hw/block/m25p80.c
>> @@ -24,7 +24,7 @@
>>  #include "hw/hw.h"
>>  #include "sysemu/block-backend.h"
>>  #include "sysemu/blockdev.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>
>>  #ifndef M25P80_ERR_DEBUG
>>  #define M25P80_ERR_DEBUG 0
>> diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
>> index 3f35369..cb82317 100644
>> --- a/hw/display/ads7846.c
>> +++ b/hw/display/ads7846.c
>> @@ -10,7 +10,7 @@
>>   * GNU GPL, version 2 or (at your option) any later version.
>>   */
>>
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "ui/console.h"
>>
>>  typedef struct {
>> diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
>> index 9727007..7545da8 100644
>> --- a/hw/display/ssd0323.c
>> +++ b/hw/display/ssd0323.c
>> @@ -10,7 +10,7 @@
>>  /* The controller can support a variety of different displays, but we
>> only
>>     implement one.  Most of the commends relating to brightness and
>> geometry
>>     setup are ignored. */
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "ui/console.h"
>>
>>  //#define DEBUG_SSD0323 1
>> diff --git a/hw/microblaze/petalogix_ml605_mmu.c
>> b/hw/microblaze/petalogix_ml605_mmu.c
>> index 462060f..5366cec 100644
>> --- a/hw/microblaze/petalogix_ml605_mmu.c
>> +++ b/hw/microblaze/petalogix_ml605_mmu.c
>> @@ -35,7 +35,7 @@
>>  #include "sysemu/block-backend.h"
>>  #include "hw/char/serial.h"
>>  #include "exec/address-spaces.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>
>>  #include "boot.h"
>>
>> diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
>> index bef3651..d619d61 100644
>> --- a/hw/misc/max111x.c
>> +++ b/hw/misc/max111x.c
>> @@ -10,7 +10,7 @@
>>   * GNU GPL, version 2 or (at your option) any later version.
>>   */
>>
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>
>>  typedef struct {
>>      SSISlave parent_obj;
>> diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
>> index e4b2d4f..4fe00fd 100644
>> --- a/hw/sd/ssi-sd.c
>> +++ b/hw/sd/ssi-sd.c
>> @@ -12,7 +12,7 @@
>>
>>  #include "sysemu/block-backend.h"
>>  #include "sysemu/blockdev.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "hw/sd.h"
>>
>>  //#define DEBUG_SSI_SD 1
>> diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c
>> index 61d568f..0bbf633 100644
>> --- a/hw/ssi/pl022.c
>> +++ b/hw/ssi/pl022.c
>> @@ -8,7 +8,7 @@
>>   */
>>
>>  #include "hw/sysbus.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>
>>  //#define DEBUG_PL022 1
>>
>> diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
>> index 2aab79b..a0f57c0 100644
>> --- a/hw/ssi/ssi.c
>> +++ b/hw/ssi/ssi.c
>> @@ -12,7 +12,7 @@
>>   * GNU GPL, version 2 or (at your option) any later version.
>>   */
>>
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>
>>  struct SSIBus {
>>      BusState parent_obj;
>> diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
>> index 620573c..94bb2a7 100644
>> --- a/hw/ssi/xilinx_spi.c
>> +++ b/hw/ssi/xilinx_spi.c
>> @@ -29,7 +29,7 @@
>>  #include "qemu/log.h"
>>  #include "qemu/fifo8.h"
>>
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>
>>  #ifdef XILINX_SPI_ERR_DEBUG
>>  #define DB_PRINT(...) do { \
>> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
>> index 0910f54..e9471ff 100644
>> --- a/hw/ssi/xilinx_spips.c
>> +++ b/hw/ssi/xilinx_spips.c
>> @@ -27,7 +27,7 @@
>>  #include "hw/ptimer.h"
>>  #include "qemu/log.h"
>>  #include "qemu/fifo8.h"
>> -#include "hw/ssi.h"
>> +#include "hw/ssi/ssi.h"
>>  #include "qemu/bitops.h"
>>
>>  #ifndef XILINX_SPIPS_ERR_DEBUG
>> diff --git a/include/hw/ssi.h b/include/hw/ssi/ssi.h
>> similarity index 96%
>> rename from include/hw/ssi.h
>> rename to include/hw/ssi/ssi.h
>> index df0f838..4a0a539 100644
>> --- a/include/hw/ssi.h
>> +++ b/include/hw/ssi/ssi.h
>> @@ -14,6 +14,8 @@
>>  #include "hw/qdev.h"
>>
>>  typedef struct SSISlave SSISlave;
>> +typedef struct SSISlaveClass SSISlaveClass;
>> +typedef enum SSICSMode SSICSMode;
>>
>>  #define TYPE_SSI_SLAVE "ssi-slave"
>>  #define SSI_SLAVE(obj) \
>> @@ -25,14 +27,14 @@ typedef struct SSISlave SSISlave;
>>
>>  #define SSI_GPIO_CS "ssi-gpio-cs"
>>
>> -typedef enum {
>> +enum SSICSMode {
>>      SSI_CS_NONE = 0,
>>      SSI_CS_LOW,
>>      SSI_CS_HIGH,
>> -} SSICSMode;
>> +};
>>
>>  /* Slave devices.  */
>> -typedef struct SSISlaveClass {
>> +struct SSISlaveClass {
>>      DeviceClass parent_class;
>>
>>      int (*init)(SSISlave *dev);
>> @@ -55,7 +57,7 @@ typedef struct SSISlaveClass {
>>       * always be called for the device for every txrx access to the
>> parent bus
>>       */
>>      uint32_t (*transfer_raw)(SSISlave *dev, uint32_t val);
>> -} SSISlaveClass;
>> +};
>>
>>  struct SSISlave {
>>      DeviceState parent_obj;
>> --
>> 2.5.0
>>
>

[Qemu-devel] [PATCH v3 3/5] xilinx_spips: Seperate the state struct into a header

[Alistair Francis]

Seperate out the XilinxSPIPS struct into a seperate header
file.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
 - Only split out required #defines
 - Prefix XLNX_SPIPS_

 hw/ssi/xilinx_spips.c         | 54 ++++---------------------------
 include/hw/ssi/xilinx_spips.h | 74 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+), 47 deletions(-)
 create mode 100644 include/hw/ssi/xilinx_spips.h

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index e9471ff..1b7b3fb 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -29,6 +29,7 @@
 #include "qemu/fifo8.h"
 #include "hw/ssi/ssi.h"
 #include "qemu/bitops.h"
+#include "hw/ssi/xilinx_spips.h"
 
 #ifndef XILINX_SPIPS_ERR_DEBUG
 #define XILINX_SPIPS_ERR_DEBUG 0
@@ -101,10 +102,6 @@
 #define R_LQSPI_STS         (0xA4 / 4)
 #define LQSPI_STS_WR_RECVD      (1 << 1)
 
-#define R_MOD_ID            (0xFC / 4)
-
-#define R_MAX (R_MOD_ID+1)
-
 /* size of TXRX FIFOs */
 #define RXFF_A          32
 #define TXFF_A          32
@@ -135,30 +132,6 @@ typedef enum {
 } FlashCMD;
 
 typedef struct {
-    SysBusDevice parent_obj;
-
-    MemoryRegion iomem;
-    MemoryRegion mmlqspi;
-
-    qemu_irq irq;
-    int irqline;
-
-    uint8_t num_cs;
-    uint8_t num_busses;
-
-    uint8_t snoop_state;
-    qemu_irq *cs_lines;
-    SSIBus **spi;
-
-    Fifo8 rx_fifo;
-    Fifo8 tx_fifo;
-
-    uint8_t num_txrx_bytes;
-
-    uint32_t regs[R_MAX];
-} XilinxSPIPS;
-
-typedef struct {
     XilinxSPIPS parent_obj;
 
     uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
@@ -174,19 +147,6 @@ typedef struct XilinxSPIPSClass {
     uint32_t tx_fifo_size;
 } XilinxSPIPSClass;
 
-#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
-#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
-
-#define XILINX_SPIPS(obj) \
-     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
-#define XILINX_SPIPS_CLASS(klass) \
-     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
-#define XILINX_SPIPS_GET_CLASS(obj) \
-     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
-
-#define XILINX_QSPIPS(obj) \
-     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
-
 static inline int num_effective_busses(XilinxSPIPS *s)
 {
     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
@@ -257,7 +217,7 @@ static void xilinx_spips_reset(DeviceState *d)
     XilinxSPIPS *s = XILINX_SPIPS(d);
 
     int i;
-    for (i = 0; i < R_MAX; i++) {
+    for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
         s->regs[i] = 0;
     }
 
@@ -269,7 +229,7 @@ static void xilinx_spips_reset(DeviceState *d)
     s->regs[R_TX_THRES] = 1;
     s->regs[R_RX_THRES] = 1;
     /* FIXME: move magic number definition somewhere sensible */
-    s->regs[R_MOD_ID] = 0x01090106;
+    s->regs[XLNX_SPIPS_R_MOD_ID] = 0x01090106;
     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
     s->snoop_state = SNOOP_CHECKING;
     xilinx_spips_update_ixr(s);
@@ -427,7 +387,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
     case R_SLAVE_IDLE_COUNT:
         mask = 0xFF;
         break;
-    case R_MOD_ID:
+    case XLNX_SPIPS_R_MOD_ID:
         mask = 0x01FFFFFF;
         break;
     case R_INTR_EN:
@@ -500,7 +460,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
         break;
     case R_RX_DATA:
     case R_INTR_MASK:
-    case R_MOD_ID:
+    case XLNX_SPIPS_R_MOD_ID:
         mask = 0;
         break;
     case R_TX_DATA:
@@ -664,7 +624,7 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp)
     }
 
     memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
-                          "spi", R_MAX*4);
+                          "spi", XLNX_SPIPS_R_MAX*4);
     sysbus_init_mmio(sbd, &s->iomem);
 
     s->irqline = -1;
@@ -708,7 +668,7 @@ static const VMStateDescription vmstate_xilinx_spips = {
     .fields = (VMStateField[]) {
         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
-        VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
+        VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
         VMSTATE_END_OF_LIST()
     }
diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
new file mode 100644
index 0000000..f01d276
--- /dev/null
+++ b/include/hw/ssi/xilinx_spips.h
@@ -0,0 +1,74 @@
+/*
+ * Header file for the Xilinx Zynq SPI controller
+ *
+ * Copyright (C) 2015 Xilinx Inc
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef XLNX_SPIPS_H
+#define XLNX_SPIPS_H
+
+#include "hw/ssi/ssi.h"
+#include "qemu/fifo8.h"
+
+typedef struct XilinxSPIPS XilinxSPIPS;
+
+#define XLNX_SPIPS_R_MOD_ID     (0xFC / 4)
+
+#define XLNX_SPIPS_R_MAX        (XLNX_SPIPS_R_MOD_ID + 1)
+
+struct XilinxSPIPS {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+    MemoryRegion mmlqspi;
+
+    qemu_irq irq;
+    int irqline;
+
+    uint8_t num_cs;
+    uint8_t num_busses;
+
+    uint8_t snoop_state;
+    qemu_irq *cs_lines;
+    SSIBus **spi;
+
+    Fifo8 rx_fifo;
+    Fifo8 tx_fifo;
+
+    uint8_t num_txrx_bytes;
+
+    uint32_t regs[XLNX_SPIPS_R_MAX];
+};
+
+#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
+#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
+
+#define XILINX_SPIPS(obj) \
+     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
+#define XILINX_SPIPS_CLASS(klass) \
+     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
+#define XILINX_SPIPS_GET_CLASS(obj) \
+     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
+
+#define XILINX_QSPIPS(obj) \
+     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
+
+#endif /* XLNX_SPIPS_H */
-- 
2.5.0

Re: [Qemu-devel] [PATCH v3 3/5] xilinx_spips: Seperate the state struct into a header

[Peter Crosthwaite]

[-- Attachment #1: Type: text/plain, Size: 7594 bytes --]

On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
alistair.francis@xilinx.com> wrote:

> Seperate out the XilinxSPIPS struct into a seperate header
> file.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V2:
>  - Only split out required #defines
>  - Prefix XLNX_SPIPS_
>
>  hw/ssi/xilinx_spips.c         | 54 ++++---------------------------
>  include/hw/ssi/xilinx_spips.h | 74
> +++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 81 insertions(+), 47 deletions(-)
>  create mode 100644 include/hw/ssi/xilinx_spips.h
>
> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
> index e9471ff..1b7b3fb 100644
> --- a/hw/ssi/xilinx_spips.c
> +++ b/hw/ssi/xilinx_spips.c
> @@ -29,6 +29,7 @@
>  #include "qemu/fifo8.h"
>  #include "hw/ssi/ssi.h"
>  #include "qemu/bitops.h"
> +#include "hw/ssi/xilinx_spips.h"
>
>  #ifndef XILINX_SPIPS_ERR_DEBUG
>  #define XILINX_SPIPS_ERR_DEBUG 0
> @@ -101,10 +102,6 @@
>  #define R_LQSPI_STS         (0xA4 / 4)
>  #define LQSPI_STS_WR_RECVD      (1 << 1)
>
> -#define R_MOD_ID            (0xFC / 4)
> -
> -#define R_MAX (R_MOD_ID+1)
> -
>  /* size of TXRX FIFOs */
>  #define RXFF_A          32
>  #define TXFF_A          32
> @@ -135,30 +132,6 @@ typedef enum {
>  } FlashCMD;
>
>  typedef struct {
> -    SysBusDevice parent_obj;
> -
> -    MemoryRegion iomem;
> -    MemoryRegion mmlqspi;
> -
> -    qemu_irq irq;
> -    int irqline;
> -
> -    uint8_t num_cs;
> -    uint8_t num_busses;
> -
> -    uint8_t snoop_state;
> -    qemu_irq *cs_lines;
> -    SSIBus **spi;
> -
> -    Fifo8 rx_fifo;
> -    Fifo8 tx_fifo;
> -
> -    uint8_t num_txrx_bytes;
> -
> -    uint32_t regs[R_MAX];
> -} XilinxSPIPS;
> -
> -typedef struct {
>      XilinxSPIPS parent_obj;
>
>      uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
> @@ -174,19 +147,6 @@ typedef struct XilinxSPIPSClass {
>      uint32_t tx_fifo_size;
>  } XilinxSPIPSClass;
>
> -#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
> -#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
> -
> -#define XILINX_SPIPS(obj) \
> -     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
> -#define XILINX_SPIPS_CLASS(klass) \
> -     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
> -#define XILINX_SPIPS_GET_CLASS(obj) \
> -     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
> -
> -#define XILINX_QSPIPS(obj) \
> -     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
> -
>  static inline int num_effective_busses(XilinxSPIPS *s)
>  {
>      return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
> @@ -257,7 +217,7 @@ static void xilinx_spips_reset(DeviceState *d)
>      XilinxSPIPS *s = XILINX_SPIPS(d);
>
>      int i;
> -    for (i = 0; i < R_MAX; i++) {
> +    for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
>          s->regs[i] = 0;
>      }
>
> @@ -269,7 +229,7 @@ static void xilinx_spips_reset(DeviceState *d)
>      s->regs[R_TX_THRES] = 1;
>      s->regs[R_RX_THRES] = 1;
>      /* FIXME: move magic number definition somewhere sensible */
> -    s->regs[R_MOD_ID] = 0x01090106;
> +    s->regs[XLNX_SPIPS_R_MOD_ID] = 0x01090106;
>      s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
>      s->snoop_state = SNOOP_CHECKING;
>      xilinx_spips_update_ixr(s);
> @@ -427,7 +387,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr
> addr,
>      case R_SLAVE_IDLE_COUNT:
>          mask = 0xFF;
>          break;
> -    case R_MOD_ID:
> +    case XLNX_SPIPS_R_MOD_ID:
>          mask = 0x01FFFFFF;
>          break;
>      case R_INTR_EN:
> @@ -500,7 +460,7 @@ static void xilinx_spips_write(void *opaque, hwaddr
> addr,
>          break;
>      case R_RX_DATA:
>      case R_INTR_MASK:
> -    case R_MOD_ID:
> +    case XLNX_SPIPS_R_MOD_ID:
>          mask = 0;
>          break;
>      case R_TX_DATA:
> @@ -664,7 +624,7 @@ static void xilinx_spips_realize(DeviceState *dev,
> Error **errp)
>      }
>
>      memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
> -                          "spi", R_MAX*4);
> +                          "spi", XLNX_SPIPS_R_MAX*4);
>      sysbus_init_mmio(sbd, &s->iomem);
>
>      s->irqline = -1;
> @@ -708,7 +668,7 @@ static const VMStateDescription vmstate_xilinx_spips =
> {
>      .fields = (VMStateField[]) {
>          VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
>          VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
> -        VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
> +        VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
>          VMSTATE_UINT8(snoop_state, XilinxSPIPS),
>          VMSTATE_END_OF_LIST()
>      }
> diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
> new file mode 100644
> index 0000000..f01d276
> --- /dev/null
> +++ b/include/hw/ssi/xilinx_spips.h
> @@ -0,0 +1,74 @@
> +/*
> + * Header file for the Xilinx Zynq SPI controller
> + *
> + * Copyright (C) 2015 Xilinx Inc
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining
> a copy
> + * of this software and associated documentation files (the "Software"),
> to deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef XLNX_SPIPS_H
> +#define XLNX_SPIPS_H
> +
> +#include "hw/ssi/ssi.h"
> +#include "qemu/fifo8.h"
> +
> +typedef struct XilinxSPIPS XilinxSPIPS;
> +
> +#define XLNX_SPIPS_R_MOD_ID     (0xFC / 4)
> +
> +#define XLNX_SPIPS_R_MAX        (XLNX_SPIPS_R_MOD_ID + 1)
>

This incremental definition of R_MAX doesn't really play well with
splitting R_MAX off as you need to take both R_MAX and just the one
programmers model def to the header. It makes R_MOD_ID inconsistent with
the others. Instead I think just leave R_MOD_ID behind (without rename) in
the C file, and

#define XLNX_SPIPS_R_MAX        (0x100/4)

Regards,
Peter

+
> +struct XilinxSPIPS {
> +    SysBusDevice parent_obj;
> +
> +    MemoryRegion iomem;
> +    MemoryRegion mmlqspi;
> +
> +    qemu_irq irq;
> +    int irqline;
> +
> +    uint8_t num_cs;
> +    uint8_t num_busses;
> +
> +    uint8_t snoop_state;
> +    qemu_irq *cs_lines;
> +    SSIBus **spi;
> +
> +    Fifo8 rx_fifo;
> +    Fifo8 tx_fifo;
> +
> +    uint8_t num_txrx_bytes;
> +
> +    uint32_t regs[XLNX_SPIPS_R_MAX];
> +};
> +
> +#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
> +#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
> +
> +#define XILINX_SPIPS(obj) \
> +     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
> +#define XILINX_SPIPS_CLASS(klass) \
> +     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
> +#define XILINX_SPIPS_GET_CLASS(obj) \
> +     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
> +
> +#define XILINX_QSPIPS(obj) \
> +     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
> +
> +#endif /* XLNX_SPIPS_H */
> --
> 2.5.0
>
>

[-- Attachment #2: Type: text/html, Size: 9443 bytes --]

Re: [Qemu-devel] [PATCH v3 3/5] xilinx_spips: Seperate the state struct into a header

[Alistair Francis]

On Wed, Oct 28, 2015 at 6:47 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
>
>
> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>>
>> Seperate out the XilinxSPIPS struct into a seperate header
>> file.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> V2:
>>  - Only split out required #defines
>>  - Prefix XLNX_SPIPS_
>>
>>  hw/ssi/xilinx_spips.c         | 54 ++++---------------------------
>>  include/hw/ssi/xilinx_spips.h | 74
>> +++++++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 81 insertions(+), 47 deletions(-)
>>  create mode 100644 include/hw/ssi/xilinx_spips.h
>>
>> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
>> index e9471ff..1b7b3fb 100644
>> --- a/hw/ssi/xilinx_spips.c
>> +++ b/hw/ssi/xilinx_spips.c
>> @@ -29,6 +29,7 @@
>>  #include "qemu/fifo8.h"
>>  #include "hw/ssi/ssi.h"
>>  #include "qemu/bitops.h"
>> +#include "hw/ssi/xilinx_spips.h"
>>
>>  #ifndef XILINX_SPIPS_ERR_DEBUG
>>  #define XILINX_SPIPS_ERR_DEBUG 0
>> @@ -101,10 +102,6 @@
>>  #define R_LQSPI_STS         (0xA4 / 4)
>>  #define LQSPI_STS_WR_RECVD      (1 << 1)
>>
>> -#define R_MOD_ID            (0xFC / 4)
>> -
>> -#define R_MAX (R_MOD_ID+1)
>> -
>>  /* size of TXRX FIFOs */
>>  #define RXFF_A          32
>>  #define TXFF_A          32
>> @@ -135,30 +132,6 @@ typedef enum {
>>  } FlashCMD;
>>
>>  typedef struct {
>> -    SysBusDevice parent_obj;
>> -
>> -    MemoryRegion iomem;
>> -    MemoryRegion mmlqspi;
>> -
>> -    qemu_irq irq;
>> -    int irqline;
>> -
>> -    uint8_t num_cs;
>> -    uint8_t num_busses;
>> -
>> -    uint8_t snoop_state;
>> -    qemu_irq *cs_lines;
>> -    SSIBus **spi;
>> -
>> -    Fifo8 rx_fifo;
>> -    Fifo8 tx_fifo;
>> -
>> -    uint8_t num_txrx_bytes;
>> -
>> -    uint32_t regs[R_MAX];
>> -} XilinxSPIPS;
>> -
>> -typedef struct {
>>      XilinxSPIPS parent_obj;
>>
>>      uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
>> @@ -174,19 +147,6 @@ typedef struct XilinxSPIPSClass {
>>      uint32_t tx_fifo_size;
>>  } XilinxSPIPSClass;
>>
>> -#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
>> -#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
>> -
>> -#define XILINX_SPIPS(obj) \
>> -     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
>> -#define XILINX_SPIPS_CLASS(klass) \
>> -     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
>> -#define XILINX_SPIPS_GET_CLASS(obj) \
>> -     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
>> -
>> -#define XILINX_QSPIPS(obj) \
>> -     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
>> -
>>  static inline int num_effective_busses(XilinxSPIPS *s)
>>  {
>>      return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
>> @@ -257,7 +217,7 @@ static void xilinx_spips_reset(DeviceState *d)
>>      XilinxSPIPS *s = XILINX_SPIPS(d);
>>
>>      int i;
>> -    for (i = 0; i < R_MAX; i++) {
>> +    for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
>>          s->regs[i] = 0;
>>      }
>>
>> @@ -269,7 +229,7 @@ static void xilinx_spips_reset(DeviceState *d)
>>      s->regs[R_TX_THRES] = 1;
>>      s->regs[R_RX_THRES] = 1;
>>      /* FIXME: move magic number definition somewhere sensible */
>> -    s->regs[R_MOD_ID] = 0x01090106;
>> +    s->regs[XLNX_SPIPS_R_MOD_ID] = 0x01090106;
>>      s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
>>      s->snoop_state = SNOOP_CHECKING;
>>      xilinx_spips_update_ixr(s);
>> @@ -427,7 +387,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr
>> addr,
>>      case R_SLAVE_IDLE_COUNT:
>>          mask = 0xFF;
>>          break;
>> -    case R_MOD_ID:
>> +    case XLNX_SPIPS_R_MOD_ID:
>>          mask = 0x01FFFFFF;
>>          break;
>>      case R_INTR_EN:
>> @@ -500,7 +460,7 @@ static void xilinx_spips_write(void *opaque, hwaddr
>> addr,
>>          break;
>>      case R_RX_DATA:
>>      case R_INTR_MASK:
>> -    case R_MOD_ID:
>> +    case XLNX_SPIPS_R_MOD_ID:
>>          mask = 0;
>>          break;
>>      case R_TX_DATA:
>> @@ -664,7 +624,7 @@ static void xilinx_spips_realize(DeviceState *dev,
>> Error **errp)
>>      }
>>
>>      memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
>> -                          "spi", R_MAX*4);
>> +                          "spi", XLNX_SPIPS_R_MAX*4);
>>      sysbus_init_mmio(sbd, &s->iomem);
>>
>>      s->irqline = -1;
>> @@ -708,7 +668,7 @@ static const VMStateDescription vmstate_xilinx_spips =
>> {
>>      .fields = (VMStateField[]) {
>>          VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
>>          VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
>> -        VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
>> +        VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
>>          VMSTATE_UINT8(snoop_state, XilinxSPIPS),
>>          VMSTATE_END_OF_LIST()
>>      }
>> diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
>> new file mode 100644
>> index 0000000..f01d276
>> --- /dev/null
>> +++ b/include/hw/ssi/xilinx_spips.h
>> @@ -0,0 +1,74 @@
>> +/*
>> + * Header file for the Xilinx Zynq SPI controller
>> + *
>> + * Copyright (C) 2015 Xilinx Inc
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef XLNX_SPIPS_H
>> +#define XLNX_SPIPS_H
>> +
>> +#include "hw/ssi/ssi.h"
>> +#include "qemu/fifo8.h"
>> +
>> +typedef struct XilinxSPIPS XilinxSPIPS;
>> +
>> +#define XLNX_SPIPS_R_MOD_ID     (0xFC / 4)
>> +
>> +#define XLNX_SPIPS_R_MAX        (XLNX_SPIPS_R_MOD_ID + 1)
>
>
> This incremental definition of R_MAX doesn't really play well with splitting
> R_MAX off as you need to take both R_MAX and just the one programmers model
> def to the header. It makes R_MOD_ID inconsistent with the others. Instead I
> think just leave R_MOD_ID behind (without rename) in the C file, and
>
> #define XLNX_SPIPS_R_MAX        (0x100/4)

Makes sense. Will fix in the next version.

Thanks,

Alistair

>
> Regards,
> Peter
>
>> +
>> +struct XilinxSPIPS {
>> +    SysBusDevice parent_obj;
>> +
>> +    MemoryRegion iomem;
>> +    MemoryRegion mmlqspi;
>> +
>> +    qemu_irq irq;
>> +    int irqline;
>> +
>> +    uint8_t num_cs;
>> +    uint8_t num_busses;
>> +
>> +    uint8_t snoop_state;
>> +    qemu_irq *cs_lines;
>> +    SSIBus **spi;
>> +
>> +    Fifo8 rx_fifo;
>> +    Fifo8 tx_fifo;
>> +
>> +    uint8_t num_txrx_bytes;
>> +
>> +    uint32_t regs[XLNX_SPIPS_R_MAX];
>> +};
>> +
>> +#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
>> +#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
>> +
>> +#define XILINX_SPIPS(obj) \
>> +     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
>> +#define XILINX_SPIPS_CLASS(klass) \
>> +     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
>> +#define XILINX_SPIPS_GET_CLASS(obj) \
>> +     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
>> +
>> +#define XILINX_QSPIPS(obj) \
>> +     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
>> +
>> +#endif /* XLNX_SPIPS_H */
>> --
>> 2.5.0
>>
>

[Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Alistair Francis]

Connect the Xilinx SPI device to the ZynqMP model.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V3:
 - Expose the SPI Bus as part of the SoC device
V2:
 - Don't connect the SPI flash to the SoC

 hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
 include/hw/arm/xlnx-zynqmp.h |  4 ++++
 2 files changed, 41 insertions(+)

diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index b36ca3d..5671d7a 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
     21, 22,
 };
 
+static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
+    0xFF040000, 0xFF050000,
+};
+
+static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
+    19, 20,
+};
+
 typedef struct XlnxZynqMPGICRegion {
     int region_index;
     uint32_t address;
@@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
 
     object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
+        object_initialize(&s->spi[i], sizeof(s->spi[i]),
+                          TYPE_XILINX_SPIPS);
+        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+    }
 }
 
 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
 
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
+        BusState *spi_bus;
+        char bus_name[6];
+
+        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
+                                "num-busses", &error_abort);
+        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+        if (err) {
+            error_propagate(errp, err);
+            return;
+        }
+
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+                           gic_spi[spi_intr[i]]);
+
+        snprintf(bus_name, 6, "spi%d", i);
+        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
+
+        /* Add the SPI buses to the SoC child bus */
+        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
+    }
 }
 
 static Property xlnx_zynqmp_props[] = {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 4005a99..6d1d2a9 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -24,6 +24,7 @@
 #include "hw/char/cadence_uart.h"
 #include "hw/ide/pci.h"
 #include "hw/ide/ahci.h"
+#include "hw/ssi/xilinx_spips.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -33,6 +34,8 @@
 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
 #define XLNX_ZYNQMP_NUM_GEMS 4
 #define XLNX_ZYNQMP_NUM_UARTS 2
+#define XLNX_ZYNQMP_NUM_SPIS 2
+#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
 
 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
@@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
     CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
     CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
     SysbusAHCIState sata;
+    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
-- 
2.5.0

Re: [Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Peter Crosthwaite]

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On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
alistair.francis@xilinx.com> wrote:

> Connect the Xilinx SPI device to the ZynqMP model.
>
>
"devices"


> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V3:
>  - Expose the SPI Bus as part of the SoC device
> V2:
>  - Don't connect the SPI flash to the SoC
>
>  hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
>  include/hw/arm/xlnx-zynqmp.h |  4 ++++
>  2 files changed, 41 insertions(+)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index b36ca3d..5671d7a 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
>      21, 22,
>  };
>
> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
> +    0xFF040000, 0xFF050000,
> +};
> +
> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
> +    19, 20,
> +};
> +
>  typedef struct XlnxZynqMPGICRegion {
>      int region_index;
>      uint32_t address;
> @@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
>
>      object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>      qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
> +
> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
> +                          TYPE_XILINX_SPIPS);
> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> +    }
>  }
>
>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> @@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
> Error **errp)
>
>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
>      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
> +
> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
> +        BusState *spi_bus;
> +        char bus_name[6];
> +
> +        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
> +                                "num-busses", &error_abort);
>

The number of busses-per-controller is unrelated to the number of
controllers. Setting num_busses != 1 is primarily a QSPI thing, so should
this just default to 1? I think you can drop this setter completely.


> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
> &err);
> +        if (err) {
> +            error_propagate(errp, err);
> +            return;
> +        }
> +
> +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
> +                           gic_spi[spi_intr[i]]);
> +
> +        snprintf(bus_name, 6, "spi%d", i);
> +        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
> +
> +        /* Add the SPI buses to the SoC child bus */
> +        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
>

Nice! That is pretty simple in the end. One, question though, what happen
with info qtree? Do you get doubles because the bus is double parented?

I think this concept also might apply to the DP/DPDMA work, where the
display port (or AUX bus?) should be put on the SoC container. Then the
machine model (ep108) is responsible for detecting if the user wants a
display and connecting it. I.e. the DP controller shouldn't be doing the UI
init.


> +    }
>  }
>
>  static Property xlnx_zynqmp_props[] = {
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 4005a99..6d1d2a9 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -24,6 +24,7 @@
>  #include "hw/char/cadence_uart.h"
>  #include "hw/ide/pci.h"
>  #include "hw/ide/ahci.h"
> +#include "hw/ssi/xilinx_spips.h"
>
>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
> @@ -33,6 +34,8 @@
>  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
>  #define XLNX_ZYNQMP_NUM_GEMS 4
>  #define XLNX_ZYNQMP_NUM_UARTS 2
> +#define XLNX_ZYNQMP_NUM_SPIS 2
>


> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
>

NUM_SPI_FLASHES is local to ep108 so it should just be in ep108.c

Regards,
Peter


>
>  #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
>  #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>      SysbusAHCIState sata;
> +    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
>
>      char *boot_cpu;
>      ARMCPU *boot_cpu_ptr;
> --
> 2.5.0
>
>

[-- Attachment #2: Type: text/html, Size: 6516 bytes --]

Re: [Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Frederic Konrad]

On 29/10/2015 03:00, Peter Crosthwaite wrote:
> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
> alistair.francis@xilinx.com> wrote:
>
>> Connect the Xilinx SPI device to the ZynqMP model.
>>
>>
> "devices"
>
>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> V3:
>>  - Expose the SPI Bus as part of the SoC device
>> V2:
>>  - Don't connect the SPI flash to the SoC
>>
>>  hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
>>  include/hw/arm/xlnx-zynqmp.h |  4 ++++
>>  2 files changed, 41 insertions(+)
>>
>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>> index b36ca3d..5671d7a 100644
>> --- a/hw/arm/xlnx-zynqmp.c
>> +++ b/hw/arm/xlnx-zynqmp.c
>> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
>>      21, 22,
>>  };
>>
>> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
>> +    0xFF040000, 0xFF050000,
>> +};
>> +
>> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
>> +    19, 20,
>> +};
>> +
>>  typedef struct XlnxZynqMPGICRegion {
>>      int region_index;
>>      uint32_t address;
>> @@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
>>
>>      object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>>      qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>> +
>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
>> +                          TYPE_XILINX_SPIPS);
>> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>> +    }
>>  }
>>
>>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>> @@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
>> Error **errp)
>>
>>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
>>      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
>> +
>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>> +        BusState *spi_bus;
>> +        char bus_name[6];
>> +
>> +        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
>> +                                "num-busses", &error_abort);
>>
> The number of busses-per-controller is unrelated to the number of
> controllers. Setting num_busses != 1 is primarily a QSPI thing, so should
> this just default to 1? I think you can drop this setter completely.
>
>
>> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>> &err);
>> +        if (err) {
>> +            error_propagate(errp, err);
>> +            return;
>> +        }
>> +
>> +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>> +                           gic_spi[spi_intr[i]]);
>> +
>> +        snprintf(bus_name, 6, "spi%d", i);
>> +        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
>> +
>> +        /* Add the SPI buses to the SoC child bus */
>> +        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
>>
> Nice! That is pretty simple in the end. One, question though, what happen
> with info qtree? Do you get doubles because the bus is double parented?
>
> I think this concept also might apply to the DP/DPDMA work, where the
> display port (or AUX bus?) should be put on the SoC container. Then the
> machine model (ep108) is responsible for detecting if the user wants a
> display and connecting it. I.e. the DP controller shouldn't be doing the UI
> init.

You mean get the AUX and I2C bus here and connect the edid and the dpcd?
I can take a look.

Fred
>
>> +    }
>>  }
>>
>>  static Property xlnx_zynqmp_props[] = {
>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>> index 4005a99..6d1d2a9 100644
>> --- a/include/hw/arm/xlnx-zynqmp.h
>> +++ b/include/hw/arm/xlnx-zynqmp.h
>> @@ -24,6 +24,7 @@
>>  #include "hw/char/cadence_uart.h"
>>  #include "hw/ide/pci.h"
>>  #include "hw/ide/ahci.h"
>> +#include "hw/ssi/xilinx_spips.h"
>>
>>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>> @@ -33,6 +34,8 @@
>>  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
>>  #define XLNX_ZYNQMP_NUM_GEMS 4
>>  #define XLNX_ZYNQMP_NUM_UARTS 2
>> +#define XLNX_ZYNQMP_NUM_SPIS 2
>>
>
>> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
>>
> NUM_SPI_FLASHES is local to ep108 so it should just be in ep108.c
>
> Regards,
> Peter
>
>
>>  #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
>>  #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
>> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
>>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>>      SysbusAHCIState sata;
>> +    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
>>
>>      char *boot_cpu;
>>      ARMCPU *boot_cpu_ptr;
>> --
>> 2.5.0
>>
>>

Re: [Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Alistair Francis]

On Thu, Oct 29, 2015 at 1:27 AM, Frederic Konrad
<fred.konrad@greensocs.com> wrote:
> On 29/10/2015 03:00, Peter Crosthwaite wrote:
>> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
>> alistair.francis@xilinx.com> wrote:
>>
>>> Connect the Xilinx SPI device to the ZynqMP model.
>>>
>>>
>> "devices"
>>
>>
>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>> ---
>>> V3:
>>>  - Expose the SPI Bus as part of the SoC device
>>> V2:
>>>  - Don't connect the SPI flash to the SoC
>>>
>>>  hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
>>>  include/hw/arm/xlnx-zynqmp.h |  4 ++++
>>>  2 files changed, 41 insertions(+)
>>>
>>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>>> index b36ca3d..5671d7a 100644
>>> --- a/hw/arm/xlnx-zynqmp.c
>>> +++ b/hw/arm/xlnx-zynqmp.c
>>> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
>>>      21, 22,
>>>  };
>>>
>>> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
>>> +    0xFF040000, 0xFF050000,
>>> +};
>>> +
>>> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
>>> +    19, 20,
>>> +};
>>> +
>>>  typedef struct XlnxZynqMPGICRegion {
>>>      int region_index;
>>>      uint32_t address;
>>> @@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
>>>
>>>      object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>>>      qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>>> +
>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>> +                          TYPE_XILINX_SPIPS);
>>> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>> +    }
>>>  }
>>>
>>>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>>> @@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
>>> Error **errp)
>>>
>>>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
>>>      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
>>> +
>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>> +        BusState *spi_bus;
>>> +        char bus_name[6];
>>> +
>>> +        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
>>> +                                "num-busses", &error_abort);
>>>
>> The number of busses-per-controller is unrelated to the number of
>> controllers. Setting num_busses != 1 is primarily a QSPI thing, so should
>> this just default to 1? I think you can drop this setter completely.

True, but see below for a problem.

>>
>>
>>> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>>> &err);
>>> +        if (err) {
>>> +            error_propagate(errp, err);
>>> +            return;
>>> +        }
>>> +
>>> +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>> +                           gic_spi[spi_intr[i]]);
>>> +
>>> +        snprintf(bus_name, 6, "spi%d", i);
>>> +        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
>>> +
>>> +        /* Add the SPI buses to the SoC child bus */
>>> +        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
>>>
>> Nice! That is pretty simple in the end. One, question though, what happen
>> with info qtree? Do you get doubles because the bus is double parented?

I don't see the double parent problem, but I do see another problem.
I was doing it a little wrong with the multiple buses.

When I assign the SPI bus to the SoC, the more recent one replaces the
previous one. I didn't notice it before because I had two buses (which
meant they had different names) so it ended up working.

Now with only one bus per I2C they both have the same name and conflict.

I can't change the name of the bus either, so this is a bit of a problem.

I can't see a way around this, while still assigning the buses to the
SoC. I guess the best option would be to not just take the first match
when calling qdev_get_child_bus(). Which would mean implementing that
function manually. How does that sound?

Thanks,

Alistair

>>
>> I think this concept also might apply to the DP/DPDMA work, where the
>> display port (or AUX bus?) should be put on the SoC container. Then the
>> machine model (ep108) is responsible for detecting if the user wants a
>> display and connecting it. I.e. the DP controller shouldn't be doing the UI
>> init.
>
> You mean get the AUX and I2C bus here and connect the edid and the dpcd?
> I can take a look.
>
> Fred
>>
>>> +    }
>>>  }
>>>
>>>  static Property xlnx_zynqmp_props[] = {
>>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>>> index 4005a99..6d1d2a9 100644
>>> --- a/include/hw/arm/xlnx-zynqmp.h
>>> +++ b/include/hw/arm/xlnx-zynqmp.h
>>> @@ -24,6 +24,7 @@
>>>  #include "hw/char/cadence_uart.h"
>>>  #include "hw/ide/pci.h"
>>>  #include "hw/ide/ahci.h"
>>> +#include "hw/ssi/xilinx_spips.h"
>>>
>>>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>>>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>>> @@ -33,6 +34,8 @@
>>>  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
>>>  #define XLNX_ZYNQMP_NUM_GEMS 4
>>>  #define XLNX_ZYNQMP_NUM_UARTS 2
>>> +#define XLNX_ZYNQMP_NUM_SPIS 2
>>>
>>
>>> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
>>>
>> NUM_SPI_FLASHES is local to ep108 so it should just be in ep108.c
>>
>> Regards,
>> Peter
>>
>>
>>>  #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
>>>  #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
>>> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
>>>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>>>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>>>      SysbusAHCIState sata;
>>> +    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
>>>
>>>      char *boot_cpu;
>>>      ARMCPU *boot_cpu_ptr;
>>> --
>>> 2.5.0
>>>
>>>
>
>

Re: [Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Alistair Francis]

On Thu, Oct 29, 2015 at 10:45 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Thu, Oct 29, 2015 at 1:27 AM, Frederic Konrad
> <fred.konrad@greensocs.com> wrote:
>> On 29/10/2015 03:00, Peter Crosthwaite wrote:
>>> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
>>> alistair.francis@xilinx.com> wrote:
>>>
>>>> Connect the Xilinx SPI device to the ZynqMP model.
>>>>
>>>>
>>> "devices"
>>>
>>>
>>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>>> ---
>>>> V3:
>>>>  - Expose the SPI Bus as part of the SoC device
>>>> V2:
>>>>  - Don't connect the SPI flash to the SoC
>>>>
>>>>  hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
>>>>  include/hw/arm/xlnx-zynqmp.h |  4 ++++
>>>>  2 files changed, 41 insertions(+)
>>>>
>>>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>>>> index b36ca3d..5671d7a 100644
>>>> --- a/hw/arm/xlnx-zynqmp.c
>>>> +++ b/hw/arm/xlnx-zynqmp.c
>>>> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
>>>>      21, 22,
>>>>  };
>>>>
>>>> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>> +    0xFF040000, 0xFF050000,
>>>> +};
>>>> +
>>>> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>> +    19, 20,
>>>> +};
>>>> +
>>>>  typedef struct XlnxZynqMPGICRegion {
>>>>      int region_index;
>>>>      uint32_t address;
>>>> @@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
>>>>
>>>>      object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>>>>      qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>>>> +
>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>>> +                          TYPE_XILINX_SPIPS);
>>>> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>>> +    }
>>>>  }
>>>>
>>>>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>>>> @@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
>>>> Error **errp)
>>>>
>>>>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
>>>>      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
>>>> +
>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>> +        BusState *spi_bus;
>>>> +        char bus_name[6];
>>>> +
>>>> +        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
>>>> +                                "num-busses", &error_abort);
>>>>
>>> The number of busses-per-controller is unrelated to the number of
>>> controllers. Setting num_busses != 1 is primarily a QSPI thing, so should
>>> this just default to 1? I think you can drop this setter completely.
>
> True, but see below for a problem.
>
>>>
>>>
>>>> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>>>> &err);
>>>> +        if (err) {
>>>> +            error_propagate(errp, err);
>>>> +            return;
>>>> +        }
>>>> +
>>>> +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>>> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>>> +                           gic_spi[spi_intr[i]]);
>>>> +
>>>> +        snprintf(bus_name, 6, "spi%d", i);
>>>> +        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
>>>> +
>>>> +        /* Add the SPI buses to the SoC child bus */
>>>> +        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
>>>>
>>> Nice! That is pretty simple in the end. One, question though, what happen
>>> with info qtree? Do you get doubles because the bus is double parented?
>
> I don't see the double parent problem, but I do see another problem.
> I was doing it a little wrong with the multiple buses.
>
> When I assign the SPI bus to the SoC, the more recent one replaces the
> previous one. I didn't notice it before because I had two buses (which
> meant they had different names) so it ended up working.
>
> Now with only one bus per I2C they both have the same name and conflict.
>
> I can't change the name of the bus either, so this is a bit of a problem.
>
> I can't see a way around this, while still assigning the buses to the
> SoC. I guess the best option would be to not just take the first match
> when calling qdev_get_child_bus(). Which would mean implementing that
> function manually. How does that sound?

Ok, it isn't actually too bad. This is the diff I have (it's still a
little hacky):

diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index 9ac6e6f..d59cec0 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -63,18 +63,17 @@ static void xlnx_ep108_init(MachineState *machine)

     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
         SSIBus *spi_bus;
-        char bus_name[6];

-        snprintf(bus_name, 6, "spi%d", i);
-        spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
+        fprintf(stderr, "SPI device %d, bus 0\n", i);
+
+        spi_bus = (SSIBus *)qdev_get_num_child_bus(DEVICE(&s->soc), "spi0", i);

         for (j = 0; j < XLNX_ZYNQMP_NUM_SPI_FLASHES; ++j) {
             DeviceState *flash_dev = ssi_create_slave(spi_bus, "sst25wf080");
             qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev,
                                                       SSI_GPIO_CS, 0);

-            sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]),
-                               i * XLNX_ZYNQMP_NUM_SPI_FLASHES + j,
+            sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), j,
                                cs_line);
         }
     }
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index d2daf80..bc497fa 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -275,7 +275,6 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
Error **errp)

     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
         BusState *spi_bus;
-        char bus_name[6];

         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
         if (err) {
@@ -287,8 +286,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
Error **errp)
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
                            gic_spi[spi_intr[i]]);

-        snprintf(bus_name, 6, "spi%d", i);
-        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
+        spi_bus = qdev_get_child_bus(DEVICE(&s->spi[i]), "spi0");

         /* Add the SPI buses to the SoC child bus */
         QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index 4ab04aa..a831985 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -573,18 +573,27 @@ void qdev_pass_gpios(DeviceState *dev,
DeviceState *container,
     QLIST_INSERT_HEAD(&container->gpios, ngl, node);
 }

-BusState *qdev_get_child_bus(DeviceState *dev, const char *name)
+BusState *qdev_get_num_child_bus(DeviceState *dev, const char *name, int num)
 {
     BusState *bus;

     QLIST_FOREACH(bus, &dev->child_bus, sibling) {
         if (strcmp(name, bus->name) == 0) {
-            return bus;
+            if (!num) {
+                return bus;
+            } else {
+                num--;
+            }
         }
     }
     return NULL;
 }

+BusState *qdev_get_child_bus(DeviceState *dev, const char *name)
+{
+    return qdev_get_num_child_bus(dev, name, 0);
+}
+
 int qbus_walk_children(BusState *bus,
                        qdev_walkerfn *pre_devfn, qbus_walkerfn *pre_busfn,
                        qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn,
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 8057aed..2650e6f 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -295,6 +295,7 @@ qemu_irq qdev_get_gpio_out_connector(DeviceState
*dev, const char *name, int n);
 qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt,
                                  const char *name, int n);

+BusState *qdev_get_num_child_bus(DeviceState *dev, const char *name, int num);
 BusState *qdev_get_child_bus(DeviceState *dev, const char *name);

 /*** Device API.  ***/


******************************

That results in this qtee for the spi devices. I'm not sure why one
bus is there twice, but hopefully it is an easy fix.

bus: main-system-bus
  type System
  dev: xlnx.ps7-spi, id ""
    gpio-out "sysbus-irq" 5
    num-busses = 1 (0x1)
    num-ss-bits = 4 (0x4)
    num-txrx-bytes = 1 (0x1)
    mmio 00000000ff050000/0000000000000100
    bus: spi0
      type SSI
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
    bus: spi0
      type SSI
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
  dev: xlnx.ps7-spi, id ""
    gpio-out "sysbus-irq" 5
    num-busses = 1 (0x1)
    num-ss-bits = 4 (0x4)
    num-txrx-bytes = 1 (0x1)
    mmio 00000000ff040000/0000000000000100
    bus: spi0
      type SSI
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1


Thanks,

Alistair

>
> Thanks,
>
> Alistair
>
>>>
>>> I think this concept also might apply to the DP/DPDMA work, where the
>>> display port (or AUX bus?) should be put on the SoC container. Then the
>>> machine model (ep108) is responsible for detecting if the user wants a
>>> display and connecting it. I.e. the DP controller shouldn't be doing the UI
>>> init.
>>
>> You mean get the AUX and I2C bus here and connect the edid and the dpcd?
>> I can take a look.
>>
>> Fred
>>>
>>>> +    }
>>>>  }
>>>>
>>>>  static Property xlnx_zynqmp_props[] = {
>>>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>>>> index 4005a99..6d1d2a9 100644
>>>> --- a/include/hw/arm/xlnx-zynqmp.h
>>>> +++ b/include/hw/arm/xlnx-zynqmp.h
>>>> @@ -24,6 +24,7 @@
>>>>  #include "hw/char/cadence_uart.h"
>>>>  #include "hw/ide/pci.h"
>>>>  #include "hw/ide/ahci.h"
>>>> +#include "hw/ssi/xilinx_spips.h"
>>>>
>>>>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>>>>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>>>> @@ -33,6 +34,8 @@
>>>>  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
>>>>  #define XLNX_ZYNQMP_NUM_GEMS 4
>>>>  #define XLNX_ZYNQMP_NUM_UARTS 2
>>>> +#define XLNX_ZYNQMP_NUM_SPIS 2
>>>>
>>>
>>>> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
>>>>
>>> NUM_SPI_FLASHES is local to ep108 so it should just be in ep108.c
>>>
>>> Regards,
>>> Peter
>>>
>>>
>>>>  #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
>>>>  #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
>>>> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
>>>>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>>>>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>>>>      SysbusAHCIState sata;
>>>> +    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
>>>>
>>>>      char *boot_cpu;
>>>>      ARMCPU *boot_cpu_ptr;
>>>> --
>>>> 2.5.0
>>>>
>>>>
>>
>>

Re: [Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Peter Crosthwaite]

On Thu, Oct 29, 2015 at 10:45 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Thu, Oct 29, 2015 at 1:27 AM, Frederic Konrad
> <fred.konrad@greensocs.com> wrote:
>> On 29/10/2015 03:00, Peter Crosthwaite wrote:
>>> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
>>> alistair.francis@xilinx.com> wrote:
>>>
>>>> Connect the Xilinx SPI device to the ZynqMP model.
>>>>
>>>>
>>> "devices"
>>>
>>>
>>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>>> ---
>>>> V3:
>>>>  - Expose the SPI Bus as part of the SoC device
>>>> V2:
>>>>  - Don't connect the SPI flash to the SoC
>>>>
>>>>  hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
>>>>  include/hw/arm/xlnx-zynqmp.h |  4 ++++
>>>>  2 files changed, 41 insertions(+)
>>>>
>>>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>>>> index b36ca3d..5671d7a 100644
>>>> --- a/hw/arm/xlnx-zynqmp.c
>>>> +++ b/hw/arm/xlnx-zynqmp.c
>>>> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
>>>>      21, 22,
>>>>  };
>>>>
>>>> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>> +    0xFF040000, 0xFF050000,
>>>> +};
>>>> +
>>>> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>> +    19, 20,
>>>> +};
>>>> +
>>>>  typedef struct XlnxZynqMPGICRegion {
>>>>      int region_index;
>>>>      uint32_t address;
>>>> @@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
>>>>
>>>>      object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>>>>      qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>>>> +
>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>>> +                          TYPE_XILINX_SPIPS);
>>>> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>>> +    }
>>>>  }
>>>>
>>>>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>>>> @@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
>>>> Error **errp)
>>>>
>>>>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
>>>>      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
>>>> +
>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>> +        BusState *spi_bus;
>>>> +        char bus_name[6];
>>>> +
>>>> +        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
>>>> +                                "num-busses", &error_abort);
>>>>
>>> The number of busses-per-controller is unrelated to the number of
>>> controllers. Setting num_busses != 1 is primarily a QSPI thing, so should
>>> this just default to 1? I think you can drop this setter completely.
>
> True, but see below for a problem.
>
>>>
>>>
>>>> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>>>> &err);
>>>> +        if (err) {
>>>> +            error_propagate(errp, err);
>>>> +            return;
>>>> +        }
>>>> +
>>>> +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>>> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>>> +                           gic_spi[spi_intr[i]]);
>>>> +
>>>> +        snprintf(bus_name, 6, "spi%d", i);
>>>> +        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
>>>> +
>>>> +        /* Add the SPI buses to the SoC child bus */
>>>> +        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
>>>>
>>> Nice! That is pretty simple in the end. One, question though, what happen
>>> with info qtree? Do you get doubles because the bus is double parented?
>
> I don't see the double parent problem, but I do see another problem.
> I was doing it a little wrong with the multiple buses.
>
> When I assign the SPI bus to the SoC, the more recent one replaces the
> previous one. I didn't notice it before because I had two buses (which
> meant they had different names) so it ended up working.
>

I dont thinks this would have functioned though, as it would be 1st
bus of 1st controller and 2nd bus of 2nd controller.

> Now with only one bus per I2C they both have the same name and conflict.
>
> I can't change the name of the bus either, so this is a bit of a problem.
>

Can we add this renaming capability? I think it is the right solution.

Regards,
Peter

> I can't see a way around this, while still assigning the buses to the
> SoC. I guess the best option would be to not just take the first match
> when calling qdev_get_child_bus(). Which would mean implementing that
> function manually. How does that sound?
>
> Thanks,
>
> Alistair
>
>>>
>>> I think this concept also might apply to the DP/DPDMA work, where the
>>> display port (or AUX bus?) should be put on the SoC container. Then the
>>> machine model (ep108) is responsible for detecting if the user wants a
>>> display and connecting it. I.e. the DP controller shouldn't be doing the UI
>>> init.
>>
>> You mean get the AUX and I2C bus here and connect the edid and the dpcd?
>> I can take a look.
>>
>> Fred
>>>
>>>> +    }
>>>>  }
>>>>
>>>>  static Property xlnx_zynqmp_props[] = {
>>>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>>>> index 4005a99..6d1d2a9 100644
>>>> --- a/include/hw/arm/xlnx-zynqmp.h
>>>> +++ b/include/hw/arm/xlnx-zynqmp.h
>>>> @@ -24,6 +24,7 @@
>>>>  #include "hw/char/cadence_uart.h"
>>>>  #include "hw/ide/pci.h"
>>>>  #include "hw/ide/ahci.h"
>>>> +#include "hw/ssi/xilinx_spips.h"
>>>>
>>>>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>>>>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>>>> @@ -33,6 +34,8 @@
>>>>  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
>>>>  #define XLNX_ZYNQMP_NUM_GEMS 4
>>>>  #define XLNX_ZYNQMP_NUM_UARTS 2
>>>> +#define XLNX_ZYNQMP_NUM_SPIS 2
>>>>
>>>
>>>> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
>>>>
>>> NUM_SPI_FLASHES is local to ep108 so it should just be in ep108.c
>>>
>>> Regards,
>>> Peter
>>>
>>>
>>>>  #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
>>>>  #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
>>>> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
>>>>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>>>>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>>>>      SysbusAHCIState sata;
>>>> +    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
>>>>
>>>>      char *boot_cpu;
>>>>      ARMCPU *boot_cpu_ptr;
>>>> --
>>>> 2.5.0
>>>>
>>>>
>>
>>

Re: [Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Alistair Francis]

On Thu, Oct 29, 2015 at 12:04 PM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Thu, Oct 29, 2015 at 10:45 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> On Thu, Oct 29, 2015 at 1:27 AM, Frederic Konrad
>> <fred.konrad@greensocs.com> wrote:
>>> On 29/10/2015 03:00, Peter Crosthwaite wrote:
>>>> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
>>>> alistair.francis@xilinx.com> wrote:
>>>>
>>>>> Connect the Xilinx SPI device to the ZynqMP model.
>>>>>
>>>>>
>>>> "devices"
>>>>
>>>>
>>>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>>>> ---
>>>>> V3:
>>>>>  - Expose the SPI Bus as part of the SoC device
>>>>> V2:
>>>>>  - Don't connect the SPI flash to the SoC
>>>>>
>>>>>  hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
>>>>>  include/hw/arm/xlnx-zynqmp.h |  4 ++++
>>>>>  2 files changed, 41 insertions(+)
>>>>>
>>>>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>>>>> index b36ca3d..5671d7a 100644
>>>>> --- a/hw/arm/xlnx-zynqmp.c
>>>>> +++ b/hw/arm/xlnx-zynqmp.c
>>>>> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
>>>>>      21, 22,
>>>>>  };
>>>>>
>>>>> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>>> +    0xFF040000, 0xFF050000,
>>>>> +};
>>>>> +
>>>>> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>>> +    19, 20,
>>>>> +};
>>>>> +
>>>>>  typedef struct XlnxZynqMPGICRegion {
>>>>>      int region_index;
>>>>>      uint32_t address;
>>>>> @@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
>>>>>
>>>>>      object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>>>>>      qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>>>>> +
>>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>>> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>>>> +                          TYPE_XILINX_SPIPS);
>>>>> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>>>> +    }
>>>>>  }
>>>>>
>>>>>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>>>>> @@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
>>>>> Error **errp)
>>>>>
>>>>>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
>>>>>      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
>>>>> +
>>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>>> +        BusState *spi_bus;
>>>>> +        char bus_name[6];
>>>>> +
>>>>> +        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
>>>>> +                                "num-busses", &error_abort);
>>>>>
>>>> The number of busses-per-controller is unrelated to the number of
>>>> controllers. Setting num_busses != 1 is primarily a QSPI thing, so should
>>>> this just default to 1? I think you can drop this setter completely.
>>
>> True, but see below for a problem.
>>
>>>>
>>>>
>>>>> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>>>>> &err);
>>>>> +        if (err) {
>>>>> +            error_propagate(errp, err);
>>>>> +            return;
>>>>> +        }
>>>>> +
>>>>> +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>>>> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>>>> +                           gic_spi[spi_intr[i]]);
>>>>> +
>>>>> +        snprintf(bus_name, 6, "spi%d", i);
>>>>> +        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
>>>>> +
>>>>> +        /* Add the SPI buses to the SoC child bus */
>>>>> +        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
>>>>>
>>>> Nice! That is pretty simple in the end. One, question though, what happen
>>>> with info qtree? Do you get doubles because the bus is double parented?
>>
>> I don't see the double parent problem, but I do see another problem.
>> I was doing it a little wrong with the multiple buses.
>>
>> When I assign the SPI bus to the SoC, the more recent one replaces the
>> previous one. I didn't notice it before because I had two buses (which
>> meant they had different names) so it ended up working.
>>
>
> I dont thinks this would have functioned though, as it would be 1st
> bus of 1st controller and 2nd bus of 2nd controller.
>
>> Now with only one bus per I2C they both have the same name and conflict.
>>
>> I can't change the name of the bus either, so this is a bit of a problem.
>>
>
> Can we add this renaming capability? I think it is the right solution.

Renaming the bus is pretty easy. There is still a qtree problem though.

For some reason SPI0 gets attached to the second SPI controller and I
can't figure it out.

bus: main-system-bus
  type System
  dev: xlnx.ps7-spi, id ""
    gpio-out "sysbus-irq" 5
    num-busses = 1 (0x1)
    num-ss-bits = 4 (0x4)
    num-txrx-bytes = 1 (0x1)
    mmio 00000000ff050000/0000000000000100
    bus: spi1
      type SSI
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
    bus: spi0
      type SSI
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
  dev: xlnx.ps7-spi, id ""
    gpio-out "sysbus-irq" 5
    num-busses = 1 (0x1)
    num-ss-bits = 4 (0x4)
    num-txrx-bytes = 1 (0x1)
    mmio 00000000ff040000/0000000000000100
    bus: spi0
      type SSI
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1
      dev: sst25wf080, id ""
        gpio-in "ssi-gpio-cs" 1

Thanks,

Alistair

>
> Regards,
> Peter
>
>> I can't see a way around this, while still assigning the buses to the
>> SoC. I guess the best option would be to not just take the first match
>> when calling qdev_get_child_bus(). Which would mean implementing that
>> function manually. How does that sound?
>>
>> Thanks,
>>
>> Alistair
>>
>>>>
>>>> I think this concept also might apply to the DP/DPDMA work, where the
>>>> display port (or AUX bus?) should be put on the SoC container. Then the
>>>> machine model (ep108) is responsible for detecting if the user wants a
>>>> display and connecting it. I.e. the DP controller shouldn't be doing the UI
>>>> init.
>>>
>>> You mean get the AUX and I2C bus here and connect the edid and the dpcd?
>>> I can take a look.
>>>
>>> Fred
>>>>
>>>>> +    }
>>>>>  }
>>>>>
>>>>>  static Property xlnx_zynqmp_props[] = {
>>>>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>>>>> index 4005a99..6d1d2a9 100644
>>>>> --- a/include/hw/arm/xlnx-zynqmp.h
>>>>> +++ b/include/hw/arm/xlnx-zynqmp.h
>>>>> @@ -24,6 +24,7 @@
>>>>>  #include "hw/char/cadence_uart.h"
>>>>>  #include "hw/ide/pci.h"
>>>>>  #include "hw/ide/ahci.h"
>>>>> +#include "hw/ssi/xilinx_spips.h"
>>>>>
>>>>>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>>>>>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>>>>> @@ -33,6 +34,8 @@
>>>>>  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
>>>>>  #define XLNX_ZYNQMP_NUM_GEMS 4
>>>>>  #define XLNX_ZYNQMP_NUM_UARTS 2
>>>>> +#define XLNX_ZYNQMP_NUM_SPIS 2
>>>>>
>>>>
>>>>> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
>>>>>
>>>> NUM_SPI_FLASHES is local to ep108 so it should just be in ep108.c
>>>>
>>>> Regards,
>>>> Peter
>>>>
>>>>
>>>>>  #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
>>>>>  #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
>>>>> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
>>>>>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>>>>>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>>>>>      SysbusAHCIState sata;
>>>>> +    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
>>>>>
>>>>>      char *boot_cpu;
>>>>>      ARMCPU *boot_cpu_ptr;
>>>>> --
>>>>> 2.5.0
>>>>>
>>>>>
>>>
>>>
>

Re: [Qemu-devel] [PATCH v3 4/5] xlnx-zynqmp: Connect the SPI devices

[Alistair Francis]

On Fri, Oct 30, 2015 at 3:21 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Thu, Oct 29, 2015 at 12:04 PM, Peter Crosthwaite
> <crosthwaitepeter@gmail.com> wrote:
>> On Thu, Oct 29, 2015 at 10:45 AM, Alistair Francis
>> <alistair.francis@xilinx.com> wrote:
>>> On Thu, Oct 29, 2015 at 1:27 AM, Frederic Konrad
>>> <fred.konrad@greensocs.com> wrote:
>>>> On 29/10/2015 03:00, Peter Crosthwaite wrote:
>>>>> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
>>>>> alistair.francis@xilinx.com> wrote:
>>>>>
>>>>>> Connect the Xilinx SPI device to the ZynqMP model.
>>>>>>
>>>>>>
>>>>> "devices"
>>>>>
>>>>>
>>>>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>>>>> ---
>>>>>> V3:
>>>>>>  - Expose the SPI Bus as part of the SoC device
>>>>>> V2:
>>>>>>  - Don't connect the SPI flash to the SoC
>>>>>>
>>>>>>  hw/arm/xlnx-zynqmp.c         | 37 +++++++++++++++++++++++++++++++++++++
>>>>>>  include/hw/arm/xlnx-zynqmp.h |  4 ++++
>>>>>>  2 files changed, 41 insertions(+)
>>>>>>
>>>>>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>>>>>> index b36ca3d..5671d7a 100644
>>>>>> --- a/hw/arm/xlnx-zynqmp.c
>>>>>> +++ b/hw/arm/xlnx-zynqmp.c
>>>>>> @@ -48,6 +48,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
>>>>>>      21, 22,
>>>>>>  };
>>>>>>
>>>>>> +static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>>>> +    0xFF040000, 0xFF050000,
>>>>>> +};
>>>>>> +
>>>>>> +static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
>>>>>> +    19, 20,
>>>>>> +};
>>>>>> +
>>>>>>  typedef struct XlnxZynqMPGICRegion {
>>>>>>      int region_index;
>>>>>>      uint32_t address;
>>>>>> @@ -97,6 +105,12 @@ static void xlnx_zynqmp_init(Object *obj)
>>>>>>
>>>>>>      object_initialize(&s->sata, sizeof(s->sata), TYPE_SYSBUS_AHCI);
>>>>>>      qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
>>>>>> +
>>>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>>>> +        object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>>>>> +                          TYPE_XILINX_SPIPS);
>>>>>> +        qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>>>>> +    }
>>>>>>  }
>>>>>>
>>>>>>  static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>>>>>> @@ -258,6 +272,29 @@ static void xlnx_zynqmp_realize(DeviceState *dev,
>>>>>> Error **errp)
>>>>>>
>>>>>>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, SATA_ADDR);
>>>>>>      sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, gic_spi[SATA_INTR]);
>>>>>> +
>>>>>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>>>>>> +        BusState *spi_bus;
>>>>>> +        char bus_name[6];
>>>>>> +
>>>>>> +        object_property_set_int(OBJECT(&s->spi[i]), XLNX_ZYNQMP_NUM_SPIS,
>>>>>> +                                "num-busses", &error_abort);
>>>>>>
>>>>> The number of busses-per-controller is unrelated to the number of
>>>>> controllers. Setting num_busses != 1 is primarily a QSPI thing, so should
>>>>> this just default to 1? I think you can drop this setter completely.
>>>
>>> True, but see below for a problem.
>>>
>>>>>
>>>>>
>>>>>> +        object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>>>>>> &err);
>>>>>> +        if (err) {
>>>>>> +            error_propagate(errp, err);
>>>>>> +            return;
>>>>>> +        }
>>>>>> +
>>>>>> +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>>>>> +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>>>>> +                           gic_spi[spi_intr[i]]);
>>>>>> +
>>>>>> +        snprintf(bus_name, 6, "spi%d", i);
>>>>>> +        spi_bus = qdev_get_child_bus(DEVICE(&s->spi), bus_name);
>>>>>> +
>>>>>> +        /* Add the SPI buses to the SoC child bus */
>>>>>> +        QLIST_INSERT_HEAD(&dev->child_bus, spi_bus, sibling);
>>>>>>
>>>>> Nice! That is pretty simple in the end. One, question though, what happen
>>>>> with info qtree? Do you get doubles because the bus is double parented?
>>>
>>> I don't see the double parent problem, but I do see another problem.
>>> I was doing it a little wrong with the multiple buses.
>>>
>>> When I assign the SPI bus to the SoC, the more recent one replaces the
>>> previous one. I didn't notice it before because I had two buses (which
>>> meant they had different names) so it ended up working.
>>>
>>
>> I dont thinks this would have functioned though, as it would be 1st
>> bus of 1st controller and 2nd bus of 2nd controller.
>>
>>> Now with only one bus per I2C they both have the same name and conflict.
>>>
>>> I can't change the name of the bus either, so this is a bit of a problem.
>>>
>>
>> Can we add this renaming capability? I think it is the right solution.
>
> Renaming the bus is pretty easy. There is still a qtree problem though.
>
> For some reason SPI0 gets attached to the second SPI controller and I
> can't figure it out.

Ok, I think I have it figured out. Sending a new patch now.

Thanks,

Alistair

>
> bus: main-system-bus
>   type System
>   dev: xlnx.ps7-spi, id ""
>     gpio-out "sysbus-irq" 5
>     num-busses = 1 (0x1)
>     num-ss-bits = 4 (0x4)
>     num-txrx-bytes = 1 (0x1)
>     mmio 00000000ff050000/0000000000000100
>     bus: spi1
>       type SSI
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>     bus: spi0
>       type SSI
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>   dev: xlnx.ps7-spi, id ""
>     gpio-out "sysbus-irq" 5
>     num-busses = 1 (0x1)
>     num-ss-bits = 4 (0x4)
>     num-txrx-bytes = 1 (0x1)
>     mmio 00000000ff040000/0000000000000100
>     bus: spi0
>       type SSI
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>       dev: sst25wf080, id ""
>         gpio-in "ssi-gpio-cs" 1
>
> Thanks,
>
> Alistair
>
>>
>> Regards,
>> Peter
>>
>>> I can't see a way around this, while still assigning the buses to the
>>> SoC. I guess the best option would be to not just take the first match
>>> when calling qdev_get_child_bus(). Which would mean implementing that
>>> function manually. How does that sound?
>>>
>>> Thanks,
>>>
>>> Alistair
>>>
>>>>>
>>>>> I think this concept also might apply to the DP/DPDMA work, where the
>>>>> display port (or AUX bus?) should be put on the SoC container. Then the
>>>>> machine model (ep108) is responsible for detecting if the user wants a
>>>>> display and connecting it. I.e. the DP controller shouldn't be doing the UI
>>>>> init.
>>>>
>>>> You mean get the AUX and I2C bus here and connect the edid and the dpcd?
>>>> I can take a look.
>>>>
>>>> Fred
>>>>>
>>>>>> +    }
>>>>>>  }
>>>>>>
>>>>>>  static Property xlnx_zynqmp_props[] = {
>>>>>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>>>>>> index 4005a99..6d1d2a9 100644
>>>>>> --- a/include/hw/arm/xlnx-zynqmp.h
>>>>>> +++ b/include/hw/arm/xlnx-zynqmp.h
>>>>>> @@ -24,6 +24,7 @@
>>>>>>  #include "hw/char/cadence_uart.h"
>>>>>>  #include "hw/ide/pci.h"
>>>>>>  #include "hw/ide/ahci.h"
>>>>>> +#include "hw/ssi/xilinx_spips.h"
>>>>>>
>>>>>>  #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>>>>>>  #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>>>>>> @@ -33,6 +34,8 @@
>>>>>>  #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
>>>>>>  #define XLNX_ZYNQMP_NUM_GEMS 4
>>>>>>  #define XLNX_ZYNQMP_NUM_UARTS 2
>>>>>> +#define XLNX_ZYNQMP_NUM_SPIS 2
>>>>>>
>>>>>
>>>>>> +#define XLNX_ZYNQMP_NUM_SPI_FLASHES 4
>>>>>>
>>>>> NUM_SPI_FLASHES is local to ep108 so it should just be in ep108.c
>>>>>
>>>>> Regards,
>>>>> Peter
>>>>>
>>>>>
>>>>>>  #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
>>>>>>  #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
>>>>>> @@ -63,6 +66,7 @@ typedef struct XlnxZynqMPState {
>>>>>>      CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>>>>>>      CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>>>>>>      SysbusAHCIState sata;
>>>>>> +    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
>>>>>>
>>>>>>      char *boot_cpu;
>>>>>>      ARMCPU *boot_cpu_ptr;
>>>>>> --
>>>>>> 2.5.0
>>>>>>
>>>>>>
>>>>
>>>>
>>

[Qemu-devel] [PATCH v3 5/5] xlnx-ep108: Connect the SPI Flash

[Alistair Francis]

Connect the sst25wf080 SPI flash to the EP108 board.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V3:
 - Don't reach into the SoC
V2:
 - Use sst25wf080 instead of m25p80

 hw/arm/xlnx-ep108.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index 2899698..9ac6e6f 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -33,6 +33,7 @@ static struct arm_boot_info xlnx_ep108_binfo;
 static void xlnx_ep108_init(MachineState *machine)
 {
     XlnxEP108 *s = g_new0(XlnxEP108, 1);
+    int i, j;
     Error *err = NULL;
 
     object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
@@ -60,6 +61,24 @@ static void xlnx_ep108_init(MachineState *machine)
                                          machine->ram_size);
     memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
 
+    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
+        SSIBus *spi_bus;
+        char bus_name[6];
+
+        snprintf(bus_name, 6, "spi%d", i);
+        spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
+
+        for (j = 0; j < XLNX_ZYNQMP_NUM_SPI_FLASHES; ++j) {
+            DeviceState *flash_dev = ssi_create_slave(spi_bus, "sst25wf080");
+            qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev,
+                                                      SSI_GPIO_CS, 0);
+
+            sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]),
+                               i * XLNX_ZYNQMP_NUM_SPI_FLASHES + j,
+                               cs_line);
+        }
+    }
+
     xlnx_ep108_binfo.ram_size = machine->ram_size;
     xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
     xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
-- 
2.5.0

Re: [Qemu-devel] [PATCH v3 5/5] xlnx-ep108: Connect the SPI Flash

[Peter Crosthwaite]

[-- Attachment #1: Type: text/plain, Size: 2527 bytes --]

On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis <
alistair.francis@xilinx.com> wrote:

> Connect the sst25wf080 SPI flash to the EP108 board.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V3:
>  - Don't reach into the SoC
> V2:
>  - Use sst25wf080 instead of m25p80
>
>  hw/arm/xlnx-ep108.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
> index 2899698..9ac6e6f 100644
> --- a/hw/arm/xlnx-ep108.c
> +++ b/hw/arm/xlnx-ep108.c
> @@ -33,6 +33,7 @@ static struct arm_boot_info xlnx_ep108_binfo;
>  static void xlnx_ep108_init(MachineState *machine)
>  {
>      XlnxEP108 *s = g_new0(XlnxEP108, 1);
> +    int i, j;
>      Error *err = NULL;
>
>      object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
> @@ -60,6 +61,24 @@ static void xlnx_ep108_init(MachineState *machine)
>                                           machine->ram_size);
>      memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
>
> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
> +        SSIBus *spi_bus;
> +        char bus_name[6];
> +
> +        snprintf(bus_name, 6, "spi%d", i);
> +        spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
> +
> +        for (j = 0; j < XLNX_ZYNQMP_NUM_SPI_FLASHES; ++j) {
>


So this fully-populated 2X4 arrangement of SPI flashes is a QEMU-specific
concept that was invented before we attempted to accurately model real
boards. That is, xilinx-zynq-a9 is really a virt-only machine model with no
equivalent board (although a 702 dts goes a long way). So in the absence of
a concrete board definition, I opted for this fully-populated scheme. It
was done for software testing with multiple devs and controllers as no real
boards had multiple SPI flash chips. I don't think that should carry over
to EP108 as-is.

Regards,
Peter


> +            DeviceState *flash_dev = ssi_create_slave(spi_bus,
> "sst25wf080");
> +            qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev,
> +                                                      SSI_GPIO_CS, 0);
> +
> +            sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]),
> +                               i * XLNX_ZYNQMP_NUM_SPI_FLASHES + j,
> +                               cs_line);
> +        }
> +    }
> +
>      xlnx_ep108_binfo.ram_size = machine->ram_size;
>      xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
>      xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
> --
> 2.5.0
>
>

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Re: [Qemu-devel] [PATCH v3 5/5] xlnx-ep108: Connect the SPI Flash

[Alistair Francis]

On Thu, Oct 29, 2015 at 7:36 AM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
>
>
> On Wed, Oct 28, 2015 at 10:32 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>>
>> Connect the sst25wf080 SPI flash to the EP108 board.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>> ---
>> V3:
>>  - Don't reach into the SoC
>> V2:
>>  - Use sst25wf080 instead of m25p80
>>
>>  hw/arm/xlnx-ep108.c | 19 +++++++++++++++++++
>>  1 file changed, 19 insertions(+)
>>
>> diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
>> index 2899698..9ac6e6f 100644
>> --- a/hw/arm/xlnx-ep108.c
>> +++ b/hw/arm/xlnx-ep108.c
>> @@ -33,6 +33,7 @@ static struct arm_boot_info xlnx_ep108_binfo;
>>  static void xlnx_ep108_init(MachineState *machine)
>>  {
>>      XlnxEP108 *s = g_new0(XlnxEP108, 1);
>> +    int i, j;
>>      Error *err = NULL;
>>
>>      object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
>> @@ -60,6 +61,24 @@ static void xlnx_ep108_init(MachineState *machine)
>>                                           machine->ram_size);
>>      memory_region_add_subregion(get_system_memory(), 0, &s->ddr_ram);
>>
>> +    for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
>> +        SSIBus *spi_bus;
>> +        char bus_name[6];
>> +
>> +        snprintf(bus_name, 6, "spi%d", i);
>> +        spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc),
>> bus_name);
>> +
>> +        for (j = 0; j < XLNX_ZYNQMP_NUM_SPI_FLASHES; ++j) {
>
>
>
> So this fully-populated 2X4 arrangement of SPI flashes is a QEMU-specific
> concept that was invented before we attempted to accurately model real
> boards. That is, xilinx-zynq-a9 is really a virt-only machine model with no
> equivalent board (although a 702 dts goes a long way). So in the absence of
> a concrete board definition, I opted for this fully-populated scheme. It was
> done for software testing with multiple devs and controllers as no real
> boards had multiple SPI flash chips. I don't think that should carry over to
> EP108 as-is.

Ok, I had a deeper look and it looks like there is only one SPI flash device per
I2C device, so I have fixed that.

Thanks,

Alistair

>
> Regards,
> Peter
>
>>
>> +            DeviceState *flash_dev = ssi_create_slave(spi_bus,
>> "sst25wf080");
>> +            qemu_irq cs_line = qdev_get_gpio_in_named(flash_dev,
>> +                                                      SSI_GPIO_CS, 0);
>> +
>> +            sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]),
>> +                               i * XLNX_ZYNQMP_NUM_SPI_FLASHES + j,
>> +                               cs_line);
>> +        }
>> +    }
>> +
>>      xlnx_ep108_binfo.ram_size = machine->ram_size;
>>      xlnx_ep108_binfo.kernel_filename = machine->kernel_filename;
>>      xlnx_ep108_binfo.kernel_cmdline = machine->kernel_cmdline;
>> --
>> 2.5.0
>>
>