From: Richard Henderson <rth@twiddle.net>
To: Xiao Guangrong <guangrong.xiao@linux.intel.com>, pbonzini@redhat.com
Cc: ehabkost@redhat.com, kvm@vger.kernel.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-i386: enable cflushopt/clwb/pcommit instructions
Date: Fri, 30 Oct 2015 13:54:33 -0700 [thread overview]
Message-ID: <5633D909.3030901@twiddle.net> (raw)
In-Reply-To: <1446103899-8644-1-git-send-email-guangrong.xiao@linux.intel.com>
On 10/29/2015 12:31 AM, Xiao Guangrong wrote:
> These instructions are used by NVDIMM drivers and the specification
> locates at:
> https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf
>
> There instructions are available on Skylake Server
>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
> ---
> target-i386/cpu.c | 8 +++++---
> target-i386/cpu.h | 3 +++
> 2 files changed, 8 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
Although it would be nice to update the comments in translate.c to include the
new insns, since they overlap mfence and sfence. At present we only check for
SSE enabled when accepting these; I suppose it's easiest to consider it invalid
to specify +clwb,-sse?
r~
next prev parent reply other threads:[~2015-10-30 20:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-29 7:31 [Qemu-devel] [PATCH] target-i386: enable cflushopt/clwb/pcommit instructions Xiao Guangrong
2015-10-30 20:54 ` Richard Henderson [this message]
2015-11-04 19:35 ` Eduardo Habkost
2015-11-05 7:51 ` Richard Henderson
2015-11-05 16:36 ` Eduardo Habkost
-- strict thread matches above, loose matches on Subject: below --
2015-08-21 5:05 Xiao Guangrong
2015-08-21 16:05 ` Eduardo Habkost
2015-08-26 10:51 ` Xiao Guangrong
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