From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47345) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zto4Q-0003KX-IQ for qemu-devel@nongnu.org; Tue, 03 Nov 2015 21:45:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zto4N-0005Jf-B7 for qemu-devel@nongnu.org; Tue, 03 Nov 2015 21:45:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:59198) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zto4N-0005JP-2S for qemu-devel@nongnu.org; Tue, 03 Nov 2015 21:45:03 -0500 References: <1446549255-26172-1-git-send-email-leonid.bloch@ravellosystems.com> <1446549255-26172-4-git-send-email-leonid.bloch@ravellosystems.com> From: Jason Wang Message-ID: <56397127.1040303@redhat.com> Date: Wed, 4 Nov 2015 10:44:55 +0800 MIME-Version: 1.0 In-Reply-To: <1446549255-26172-4-git-send-email-leonid.bloch@ravellosystems.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 3/7] e1000: Trivial implementation of various MAC registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leonid Bloch , qemu-devel@nongnu.org Cc: Dmitry Fleytman , Leonid Bloch , Shmulik Ladkani On 11/03/2015 07:14 PM, Leonid Bloch wrote: > These registers appear in Intel's specs, but were not implemented. > These registers are now implemented trivially, i.e. they are initiated > with zero values, and if they are RW, they can be written or read by the > driver, or read only if they are R (essentially retaining their zero > values). For these registers no other procedures are performed. > > For the trivially implemented Diagnostic registers, a debug warning is > produced on read/write attempts. > > The registers implemented here are: > > Transmit: > RW: AIT > > Management: > RW: WUC WUS IPAV IP6AT* IP4AT* FFLT* WUPM* FFMT* FFVT* > > Diagnostic: > RW: RDFH RDFT RDFHS RDFTS RDFPC PBM* TDFH TDFT TDFHS > TDFTS TDFPC > > Statistic: > RW: FCRUC > R: RNBC TSCTFC MGTPRC MGTPDC MGTPTC RFC RJC SCC ECOL > LATECOL MCC COLC DC TNCRS SEC CEXTERR RLEC XONRXC > XONTXC XOFFRXC XOFFTXC > > Signed-off-by: Leonid Bloch > Signed-off-by: Dmitry Fleytman > --- > hw/net/e1000.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++++-- > hw/net/e1000_regs.h | 6 ++++ > 2 files changed, 98 insertions(+), 3 deletions(-) > > diff --git a/hw/net/e1000.c b/hw/net/e1000.c > index 1190bbe..7db6614 100644 > --- a/hw/net/e1000.c > +++ b/hw/net/e1000.c > @@ -170,7 +170,17 @@ enum { > defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC), > defreg(RA), defreg(MTA), defreg(CRCERRS), defreg(VFTA), > defreg(VET), defreg(RDTR), defreg(RADV), defreg(TADV), > - defreg(ITR), > + defreg(ITR), defreg(FCRUC), defreg(TDFH), defreg(TDFT), > + defreg(TDFHS), defreg(TDFTS), defreg(TDFPC), defreg(RDFH), > + defreg(RDFT), defreg(RDFHS), defreg(RDFTS), defreg(RDFPC), > + defreg(IPAV), defreg(WUC), defreg(WUS), defreg(AIT), > + defreg(IP6AT), defreg(IP4AT), defreg(FFLT), defreg(FFMT), > + defreg(FFVT), defreg(WUPM), defreg(PBM), defreg(SCC), > + defreg(ECOL), defreg(MCC), defreg(LATECOL), defreg(COLC), > + defreg(DC), defreg(TNCRS), defreg(SEC), defreg(CEXTERR), > + defreg(RLEC), defreg(XONRXC), defreg(XONTXC), defreg(XOFFRXC), > + defreg(XOFFTXC), defreg(RFC), defreg(RJC), defreg(RNBC), > + defreg(TSCTFC), defreg(MGTPRC), defreg(MGTPDC), defreg(MGTPTC) > }; > > static void > @@ -1118,6 +1128,48 @@ mac_readreg(E1000State *s, int index) > } > > static uint32_t > +mac_readreg_prt(E1000State *s, int index) > +{ > + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. " > + "It is not fully implemented.\n", index<<2); > + return s->mac_reg[index]; > +} > + > +static uint32_t > +mac_low4_read(E1000State *s, int index) > +{ > + return s->mac_reg[index] & 0xf; > +} > + > +static uint32_t > +mac_low11_read(E1000State *s, int index) > +{ > + return s->mac_reg[index] & 0x7ff; > +} > + > +static uint32_t > +mac_low11_read_prt(E1000State *s, int index) > +{ > + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. " > + "It is not fully implemented.\n", index<<2); > + return s->mac_reg[index] & 0x7ff; > +} > + > +static uint32_t > +mac_low13_read_prt(E1000State *s, int index) > +{ > + DBGOUT(GENERAL, "Reading register at offset: 0x%08x. " > + "It is not fully implemented.\n", index<<2); > + return s->mac_reg[index] & 0x1fff; > +} > + > +static uint32_t > +mac_low16_read(E1000State *s, int index) > +{ > + return s->mac_reg[index] & 0xffff; > +} > + > +static uint32_t > mac_icr_read(E1000State *s, int index) > { > uint32_t ret = s->mac_reg[ICR]; > @@ -1161,6 +1213,14 @@ mac_writereg(E1000State *s, int index, uint32_t val) > } > > static void > +mac_writereg_prt(E1000State *s, int index, uint32_t val) > +{ > + DBGOUT(GENERAL, "Writing to register at offset: 0x%08x. " > + "It is not fully implemented.\n", index<<2); > + s->mac_reg[index] = val; > +} > + > +static void > set_rdt(E1000State *s, int index, uint32_t val) > { > s->mac_reg[index] = val & 0xffff; > @@ -1219,26 +1279,50 @@ static uint32_t (*macreg_readops[])(E1000State *, int) = { > getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS), > getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL), > getreg(TDLEN), getreg(RDLEN), getreg(RDTR), getreg(RADV), > - getreg(TADV), getreg(ITR), > + getreg(TADV), getreg(ITR), getreg(FCRUC), getreg(IPAV), > + getreg(WUC), getreg(WUS), getreg(SCC), getreg(ECOL), > + getreg(MCC), getreg(LATECOL), getreg(COLC), getreg(DC), > + getreg(TNCRS), getreg(SEC), getreg(CEXTERR), getreg(RLEC), > + getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC), > + getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC), > + getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), > > [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, > [GPRC] = mac_read_clr4, [GPTC] = mac_read_clr4, > [TPT] = mac_read_clr4, [TPR] = mac_read_clr4, > [ICR] = mac_icr_read, [EECD] = get_eecd, > [EERD] = flash_eerd_read, > + [RDFH] = mac_low13_read_prt, [RDFT] = mac_low13_read_prt, > + [RDFHS] = mac_low13_read_prt, [RDFTS] = mac_low13_read_prt, > + [RDFPC] = mac_low13_read_prt, > + [TDFH] = mac_low11_read_prt, [TDFT] = mac_low11_read_prt, > + [TDFHS] = mac_low13_read_prt, [TDFTS] = mac_low13_read_prt, > + [TDFPC] = mac_low13_read_prt, > + [AIT] = mac_low16_read, > > [CRCERRS ... MPC] = &mac_readreg, > + [IP6AT ... IP6AT+3] = &mac_readreg, [IP4AT ... IP4AT+6] = &mac_readreg, > + [FFLT ... FFLT+6] = &mac_low11_read, > [RA ... RA+31] = &mac_readreg, > + [WUPM ... WUPM+31] = &mac_readreg, > [MTA ... MTA+127] = &mac_readreg, > [VFTA ... VFTA+127] = &mac_readreg, > + [FFMT ... FFMT+254] = &mac_low4_read, > + [FFVT ... FFVT+254] = &mac_readreg, > + [PBM ... PBM+16383] = &mac_readreg_prt, > }; Need to limit the function of those MAC registers to 2.5 and above (probably another flag and turn it off by default for pre 2.5) only. Otherwise, the values of those registers will be zero after migrating to old qemu.