From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39158) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZuBNv-0001Mk-9T for qemu-devel@nongnu.org; Wed, 04 Nov 2015 22:38:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZuBNp-0008Se-M4 for qemu-devel@nongnu.org; Wed, 04 Nov 2015 22:38:47 -0500 Received: from mga14.intel.com ([192.55.52.115]:60988) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZuBNp-0008SU-Ga for qemu-devel@nongnu.org; Wed, 04 Nov 2015 22:38:41 -0500 References: <1446672079-8549-1-git-send-email-ehabkost@redhat.com> From: Xiao Guangrong Message-ID: <563ACDCD.7050404@linux.intel.com> Date: Thu, 5 Nov 2015 11:32:29 +0800 MIME-Version: 1.0 In-Reply-To: <1446672079-8549-1-git-send-email-ehabkost@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [kvm-unit-test RFC] x86: Memory instructions test case List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost , qemu-devel@nongnu.org Cc: Paolo Bonzini , kvm@vger.kernel.org, Richard Henderson On 11/05/2015 05:21 AM, Eduardo Habkost wrote: > Quickly hacked test case for memory instructions (clflush, mfence, > sfence, lfence, clflushopt, clwb, pcommit), that simply checks for #UD > exceptions. > > This was useful to test TCG handling of those instructions. > > The "fake clwb" part will probably break once a new instruction use > those opcodes. Tested it on the box on that these instruction are available, it worked. Tested-by: Xiao Guangrong