From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Bharata B Rao <bharata@linux.vnet.ibm.com>,
qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, aneesh.kumar@linux.vnet.ibm.com,
david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM
Date: Tue, 10 Nov 2015 12:13:50 +1100 [thread overview]
Message-ID: <564144CE.2000603@ozlabs.ru> (raw)
In-Reply-To: <1446844375.14282.34.camel@kernel.crashing.org>
On 11/07/2015 08:12 AM, Benjamin Herrenschmidt wrote:
> On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote:
>> Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and
>> 2.07)
>> removed the mmu_model definition POWERPC_MMU_2_06a which is needed by
>> PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a.
>>
>> This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting
>> of PR KVM guest.
>
> Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases
> to no long work. Argh....
>
> We should clean up that junk. We are mixing up bit masks and an actual
> model "number" in the same field. We should make that cleaner, using
> a mask to extract the actual version and switch/case on *that*...
I like this and I wonder if Bharata is going to do this, if not, I will, I
just noticed this this patch made it to the dwg/spapr-next tree so we need
to hurry...
Bharata, got some time for this? Thanks.
>
>> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> ---
>> target-ppc/cpu.h | 6 ++++++
>> target-ppc/mmu_helper.c | 8 ++++++++
>> 2 files changed, 14 insertions(+)
>>
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index b34aed6..31c6fee 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -122,9 +122,15 @@ enum powerpc_mmu_t {
>> /* Architecture 2.06 variant */
>> POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
>> | POWERPC_MMU_AMR | 0x00000003,
>> + /* Architecture 2.06 "degraded" (no 1T segments) */
>> + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
>> + | 0x00000003,
>> /* Architecture 2.07 variant */
>> POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
>> | POWERPC_MMU_AMR | 0x00000004,
>> + /* Architecture 2.07 "degraded" (no 1T segments) */
>> + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
>> + | 0x00000004,
>> #endif /* defined(TARGET_PPC64) */
>> };
>>
>> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
>> index e52d0e5..30298d8 100644
>> --- a/target-ppc/mmu_helper.c
>> +++ b/target-ppc/mmu_helper.c
>> @@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function
>> cpu_fprintf, CPUPPCState *env)
>> case POWERPC_MMU_64B:
>> case POWERPC_MMU_2_03:
>> case POWERPC_MMU_2_06:
>> + case POWERPC_MMU_2_06a:
>> case POWERPC_MMU_2_07:
>> + case POWERPC_MMU_2_07a:
>> dump_slb(f, cpu_fprintf, env);
>> break;
>> #endif
>> @@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState
>> *cs, vaddr addr)
>> case POWERPC_MMU_64B:
>> case POWERPC_MMU_2_03:
>> case POWERPC_MMU_2_06:
>> + case POWERPC_MMU_2_06a:
>> case POWERPC_MMU_2_07:
>> + case POWERPC_MMU_2_07a:
>> return ppc_hash64_get_phys_page_debug(env, addr);
>> #endif
>>
>> @@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
>> case POWERPC_MMU_64B:
>> case POWERPC_MMU_2_03:
>> case POWERPC_MMU_2_06:
>> + case POWERPC_MMU_2_06a:
>> case POWERPC_MMU_2_07:
>> + case POWERPC_MMU_2_07a:
>> #endif /* defined(TARGET_PPC64) */
>> tlb_flush(CPU(cpu), 1);
>> break;
>> @@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env,
>> target_ulong addr)
>> case POWERPC_MMU_64B:
>> case POWERPC_MMU_2_03:
>> case POWERPC_MMU_2_06:
>> + case POWERPC_MMU_2_06a:
>> case POWERPC_MMU_2_07:
>> + case POWERPC_MMU_2_07a:
>> /* tlbie invalidate TLBs for all segments */
>> /* XXX: given the fact that there are too many segments to
>> invalidate,
>> * and we still don't have a tlb_flush_mask(env, n,
>> mask) in QEMU,
--
Alexey
next prev parent reply other threads:[~2015-11-10 1:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-06 7:42 [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM Bharata B Rao
2015-11-06 21:12 ` Benjamin Herrenschmidt
2015-11-10 1:13 ` Alexey Kardashevskiy [this message]
2015-11-10 5:29 ` Bharata B Rao
2015-11-11 0:43 ` Alexey Kardashevskiy
2015-11-11 0:46 ` David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=564144CE.2000603@ozlabs.ru \
--to=aik@ozlabs.ru \
--cc=aneesh.kumar@linux.vnet.ibm.com \
--cc=benh@kernel.crashing.org \
--cc=bharata@linux.vnet.ibm.com \
--cc=david@gibson.dropbear.id.au \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).