From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZvxVY-0006eE-Gh for qemu-devel@nongnu.org; Mon, 09 Nov 2015 20:14:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZvxVV-0003m3-9Y for qemu-devel@nongnu.org; Mon, 09 Nov 2015 20:14:00 -0500 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:33706) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZvxVU-0003kq-UW for qemu-devel@nongnu.org; Mon, 09 Nov 2015 20:13:57 -0500 Received: by pabfh17 with SMTP id fh17so216568233pab.0 for ; Mon, 09 Nov 2015 17:13:56 -0800 (PST) References: <1446795779-28086-1-git-send-email-bharata@linux.vnet.ibm.com> <1446844375.14282.34.camel@kernel.crashing.org> From: Alexey Kardashevskiy Message-ID: <564144CE.2000603@ozlabs.ru> Date: Tue, 10 Nov 2015 12:13:50 +1100 MIME-Version: 1.0 In-Reply-To: <1446844375.14282.34.camel@kernel.crashing.org> Content-Type: text/plain; charset=koi8-r; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt , Bharata B Rao , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, aneesh.kumar@linux.vnet.ibm.com, david@gibson.dropbear.id.au On 11/07/2015 08:12 AM, Benjamin Herrenschmidt wrote: > On Fri, 2015-11-06 at 13:12 +0530, Bharata B Rao wrote: >> Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and >> 2.07) >> removed the mmu_model definition POWERPC_MMU_2_06a which is needed by >> PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. >> >> This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting >> of PR KVM guest. > > Hrm, I see... we clear the 1TSEG bit and that causes the switch/cases > to no long work. Argh.... > > We should clean up that junk. We are mixing up bit masks and an actual > model "number" in the same field. We should make that cleaner, using > a mask to extract the actual version and switch/case on *that*... I like this and I wonder if Bharata is going to do this, if not, I will, I just noticed this this patch made it to the dwg/spapr-next tree so we need to hurry... Bharata, got some time for this? Thanks. > >> Signed-off-by: Bharata B Rao >> Cc: Benjamin Herrenschmidt >> --- >> target-ppc/cpu.h | 6 ++++++ >> target-ppc/mmu_helper.c | 8 ++++++++ >> 2 files changed, 14 insertions(+) >> >> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h >> index b34aed6..31c6fee 100644 >> --- a/target-ppc/cpu.h >> +++ b/target-ppc/cpu.h >> @@ -122,9 +122,15 @@ enum powerpc_mmu_t { >> /* Architecture 2.06 variant */ >> POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG >> | POWERPC_MMU_AMR | 0x00000003, >> + /* Architecture 2.06 "degraded" (no 1T segments) */ >> + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR >> + | 0x00000003, >> /* Architecture 2.07 variant */ >> POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG >> | POWERPC_MMU_AMR | 0x00000004, >> + /* Architecture 2.07 "degraded" (no 1T segments) */ >> + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR >> + | 0x00000004, >> #endif /* defined(TARGET_PPC64) */ >> }; >> >> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c >> index e52d0e5..30298d8 100644 >> --- a/target-ppc/mmu_helper.c >> +++ b/target-ppc/mmu_helper.c >> @@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function >> cpu_fprintf, CPUPPCState *env) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> dump_slb(f, cpu_fprintf, env); >> break; >> #endif >> @@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState >> *cs, vaddr addr) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> return ppc_hash64_get_phys_page_debug(env, addr); >> #endif >> >> @@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> #endif /* defined(TARGET_PPC64) */ >> tlb_flush(CPU(cpu), 1); >> break; >> @@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, >> target_ulong addr) >> case POWERPC_MMU_64B: >> case POWERPC_MMU_2_03: >> case POWERPC_MMU_2_06: >> + case POWERPC_MMU_2_06a: >> case POWERPC_MMU_2_07: >> + case POWERPC_MMU_2_07a: >> /* tlbie invalidate TLBs for all segments */ >> /* XXX: given the fact that there are too many segments to >> invalidate, >> * and we still don't have a tlb_flush_mask(env, n, >> mask) in QEMU, -- Alexey