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envelope-from=fei2.wu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.365, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/5/2024 1:58 PM, Wu, Fei wrote: > On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote: >> >> >> On 3/4/24 07:25, Fei Wu wrote: >>> The harts requirements of RISC-V server platform [1] require RVA23 ISA >>> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides >>> a virt CPU type (rvsp-ref) as compliant as possible. >>> >>> [1] >>> https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc >>> >>> Signed-off-by: Fei Wu >>> --->   hw/riscv/server_platform_ref.c |  6 +++- >>>   target/riscv/cpu-qom.h         |  1 + >>>   target/riscv/cpu.c             | 62 ++++++++++++++++++++++++++++++++++ >>>   3 files changed, 68 insertions(+), 1 deletion(-) >>> >>> diff --git a/hw/riscv/server_platform_ref.c >>> b/hw/riscv/server_platform_ref.c >>> index ae90c4b27a..52ec607cee 100644 >>> --- a/hw/riscv/server_platform_ref.c >>> +++ b/hw/riscv/server_platform_ref.c >>> @@ -1205,11 +1205,15 @@ static void >>> rvsp_ref_machine_class_init(ObjectClass *oc, void *data) >>>   { >>>       char str[128]; >>>       MachineClass *mc = MACHINE_CLASS(oc); >>> +    static const char * const valid_cpu_types[] = { >>> +        TYPE_RISCV_CPU_RVSP_REF, >>> +    }; >>>         mc->desc = "RISC-V Server SoC Reference board"; >>>       mc->init = rvsp_ref_machine_init; >>>       mc->max_cpus = RVSP_CPUS_MAX; >>> -    mc->default_cpu_type = TYPE_RISCV_CPU_BASE; >>> +    mc->default_cpu_type = TYPE_RISCV_CPU_RVSP_REF; >>> +    mc->valid_cpu_types = valid_cpu_types; >> >> I suggest introducing this patch first, then the new machine type that >> will use it as a default >> CPU. The reason is to facilitate future bisects. If we introduce the >> board first, a future bisect >> might hit the previous patch, the board will be run using RV64 instead >> of the correct CPU, and >> we'll have different results because of it. >> > Good suggestion. > >>>       mc->pci_allow_0_address = true; >>>       mc->default_nic = "e1000e"; >>>       mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; >>> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h >>> index 3670cfe6d9..adb934d19e 100644 >>> --- a/target/riscv/cpu-qom.h >>> +++ b/target/riscv/cpu-qom.h >>> @@ -49,6 +49,7 @@ >>>   #define TYPE_RISCV_CPU_SIFIVE_U54       >>> RISCV_CPU_TYPE_NAME("sifive-u54") >>>   #define TYPE_RISCV_CPU_THEAD_C906       >>> RISCV_CPU_TYPE_NAME("thead-c906") >>>   #define TYPE_RISCV_CPU_VEYRON_V1        >>> RISCV_CPU_TYPE_NAME("veyron-v1") >>> +#define TYPE_RISCV_CPU_RVSP_REF         RISCV_CPU_TYPE_NAME("rvsp-ref") >>>   #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host") >>>     OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) >>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >>> index 5ff0192c52..bc91be702b 100644 >>> --- a/target/riscv/cpu.c >>> +++ b/target/riscv/cpu.c >>> @@ -2282,6 +2282,67 @@ static void rva22s64_profile_cpu_init(Object *obj) >>>         RVA22S64.enabled = true; >>>   } >>> + >>> +static void rv64_rvsp_ref_cpu_init(Object *obj) >>> +{ >>> +    CPURISCVState *env = &RISCV_CPU(obj)->env; >>> +    RISCVCPU *cpu = RISCV_CPU(obj); >>> + >>> +    riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); >>> + >>> +    /* FIXME: change to 1.13 */ >>> +    env->priv_ver = PRIV_VERSION_1_12_0; >>> + >>> +    /* RVA22U64 */ >>> +    cpu->cfg.mmu = true; >>> +    cpu->cfg.ext_zifencei = true; >>> +    cpu->cfg.ext_zicsr = true; >>> +    cpu->cfg.ext_zicntr = true; >>> +    cpu->cfg.ext_zihpm = true; >>> +    cpu->cfg.ext_zihintpause = true; >>> +    cpu->cfg.ext_zba = true; >>> +    cpu->cfg.ext_zbb = true; >>> +    cpu->cfg.ext_zbs = true; >>> +    cpu->cfg.zic64b = true; >>> +    cpu->cfg.ext_zicbom = true; >>> +    cpu->cfg.ext_zicbop = true; >>> +    cpu->cfg.ext_zicboz = true; >>> +    cpu->cfg.cbom_blocksize = 64; >>> +    cpu->cfg.cbop_blocksize = 64; >>> +    cpu->cfg.cboz_blocksize = 64; >>> +    cpu->cfg.ext_zfhmin = true; >>> +    cpu->cfg.ext_zkt = true; >> >> You can change this whole block with: >> >> RVA22U64.enabled = true; >> >> >> riscv_cpu_add_profiles() will check if we have a profile enabled and, if >> that's the >> case, we'll enable all its extensions in the CPU. >> >> In the near future, when we implement a proper RVA23 support, we'll be >> able to just do >> a single RVA23S64.enabled = true in this cpu_init(). But for now we can >> at least declare >> RVA22U64 (perhaps RVA22S64) support for this CPU. >> Hi Daniel, I'm not sure if it's a regression or the usage has been changed. I'm not able to use '-cpu rva22s64' on latest qemu (db596ae190). -- latest qemu, cannot see linux boot message and blocked $Q -machine virt -nographic -m 2G -smp 2 \ -cpu rva22s64 \ -bios /usr/lib/riscv64-linux-gnu/opensbi/generic/fw_jump.elf \ -kernel $Kernel Boot HART ID : 1 Boot HART Domain : root Boot HART Priv Version : v1.12 Boot HART Base ISA : rv64imafdc Boot HART ISA Extensions : time Boot HART PMP Count : 0 Boot HART PMP Granularity : 0 Boot HART PMP Address Bits: 0 Boot HART MHPM Count : 16 Boot HART MIDELEG : 0x0000000000000222 Boot HART MEDELEG : 0x000000000000b109 -- latest qemu, w/o rva22s64, looks good $Q -machine virt -nographic -m 2G -smp 2 \ -bios /usr/lib/riscv64-linux-gnu/opensbi/generic/fw_jump.elf \ -kernel $Kernel Boot HART ID : 0 Boot HART Domain : root Boot HART Priv Version : v1.12 Boot HART Base ISA : rv64imafdch Boot HART ISA Extensions : time,sstc Boot HART PMP Count : 16 Boot HART PMP Granularity : 4 Boot HART PMP Address Bits: 54 Boot HART MHPM Count : 16 Boot HART MIDELEG : 0x0000000000001666 Boot HART MEDELEG : 0x0000000000f0b509 [ 0.000000] Linux version 6.8.0-rc6+ (box@riscv-sw-lvm-1) (riscv64-linux-gnu-gcc (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #17 SMP Wed Feb 28 08:38:42 UTC 2024 -- commit dfa3c4c57, patch to enable rva22s64, looks good $Q -machine virt -nographic -m 2G -smp 2 \ -cpu rva22s64 \ -bios /usr/lib/riscv64-linux-gnu/opensbi/generic/fw_jump.elf \ -kernel $Kernel Boot HART ID : 0 Boot HART Domain : root Boot HART Priv Version : v1.12 Boot HART Base ISA : rv64imafdc Boot HART ISA Extensions : time Boot HART PMP Count : 16 Boot HART PMP Granularity : 4 Boot HART PMP Address Bits: 54 Boot HART MHPM Count : 16 Boot HART MIDELEG : 0x0000000000000222 Boot HART MEDELEG : 0x000000000000b109 [ 0.000000] Linux version 6.8.0-rc6+ (box@riscv-sw-lvm-1) (riscv64-linux-gnu-gcc (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #17 SMP Wed Feb 28 08:38:42 UTC 2024 Thanks, Fei > Let me try. > > Thanks, > Fei. > >> >> Thanks, >> >> Daniel >> >> >>> + >>> +    /* RVA23U64 */ >>> +    cpu->cfg.ext_zvfhmin = true; >>> +    cpu->cfg.ext_zvbb = true; >>> +    cpu->cfg.ext_zvkt = true; >>> +    cpu->cfg.ext_zihintntl = true; >>> +    cpu->cfg.ext_zicond = true; >>> +    cpu->cfg.ext_zcb = true; >>> +    cpu->cfg.ext_zfa = true; >>> +    cpu->cfg.ext_zawrs = true; >>> + >>> +    /* RVA23S64 */ >>> +    cpu->cfg.ext_zifencei = true; >>> +    cpu->cfg.svade = true; >>> +    cpu->cfg.ext_svpbmt = true; >>> +    cpu->cfg.ext_svinval = true; >>> +    cpu->cfg.ext_svnapot = true; >>> +    cpu->cfg.ext_sstc = true; >>> +    cpu->cfg.ext_sscofpmf = true; >>> +    cpu->cfg.ext_smstateen = true; >>> + >>> +    cpu->cfg.ext_smaia = true; >>> +    cpu->cfg.ext_ssaia = true; >>> + >>> +    /* Server Platform */ >>> +#ifndef CONFIG_USER_ONLY >>> +    set_satp_mode_max_supported(cpu, VM_1_10_SV48); >>> +#endif >>> +    cpu->cfg.ext_svadu = true; >>> +    cpu->cfg.ext_zkr = true; >>> +} >>>   #endif >>>     static const gchar *riscv_gdb_arch_name(CPUState *cs) >>> @@ -2547,6 +2608,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { >>>       DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E,        MXL_RV64,  >>> rv64e_bare_cpu_init), >>>       DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64,  MXL_RV64,  >>> rva22u64_profile_cpu_init), >>>       DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64,  MXL_RV64,  >>> rva22s64_profile_cpu_init), >>> +    DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_RVSP_REF,   MXL_RV64,  >>> rv64_rvsp_ref_cpu_init), >>>   #endif >>>   }; >>>   >> >> >> -=-=-=-=-=-=-=-=-=-=-=- >> Links: You receive all messages sent to this group. >> View/Reply Online (#125): >> https://lists.riscv.org/g/tech-server-soc/message/125 >> Mute This Topic: https://lists.riscv.org/mt/104719379/7152971 >> Group Owner: tech-server-soc+owner@lists.riscv.org >> Unsubscribe: >> https://lists.riscv.org/g/tech-server-soc/leave/12737993/7152971/1793629631/xyzzy [fei2.wu@intel.com] >> -=-=-=-=-=-=-=-=-=-=-=- >> >> >