From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 2/2] target/arm: Use tcg_gen_gvec_bitsel
Date: Mon, 3 Jun 2019 13:15:57 -0500 [thread overview]
Message-ID: <56471d19-7c58-3790-84d6-e7b60f8a3b8e@linaro.org> (raw)
In-Reply-To: <CAFEAcA--wutvPH5xSRm7yNCQ9+TpjJ84qbSLTUa7YFgKnLmi=Q@mail.gmail.com>
On 5/23/19 8:30 AM, Peter Maydell wrote:
> On Thu, 23 May 2019 at 14:16, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 5/23/19 9:08 AM, Peter Maydell wrote:
>>>> Because the three different instructions perform the same operation with
>>>> reshuffled register arguments.
>>>
>>> Ah, so they do. Next question, how do I find out what the
>>> order of arguments in the above code means so I can compare
>>> it against the pseudocode expression we're implementing?
>>
>> >From tcg/README:
>>
>> * bitsel_vec v0, v1, v2, v3
>>
>> Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector.
>>
>> The "selector" is second, the first input operand.
>
> Oh, this series is based on another patchset.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
The prerequisite for this patch is now in master.
r~
prev parent reply other threads:[~2019-06-03 18:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-18 19:19 [Qemu-devel] [PATCH 0/2] target/arm: make use of new gvec expanders Richard Henderson
2019-05-18 19:19 ` [Qemu-devel] [PATCH 1/2] target/arm: Vectorize USHL and SSHL Richard Henderson
2019-05-23 12:44 ` Peter Maydell
2019-05-23 13:03 ` Peter Maydell
2019-06-03 17:23 ` Richard Henderson
2019-05-18 19:19 ` [Qemu-devel] [PATCH 2/2] target/arm: Use tcg_gen_gvec_bitsel Richard Henderson
2019-05-23 12:46 ` Peter Maydell
2019-05-23 13:02 ` Richard Henderson
2019-05-23 13:08 ` Peter Maydell
2019-05-23 13:16 ` Richard Henderson
2019-05-23 13:30 ` Peter Maydell
2019-06-03 18:15 ` Richard Henderson [this message]
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