From: Richard Henderson <rth@twiddle.net>
To: Max Reitz <mreitz@redhat.com>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Eduardo Habkost <ehabkost@redhat.com>,
Toni Nedialkov <farmdve@gmail.com>
Subject: Re: [Qemu-devel] [PATCH] target-i386: Fix mulx for identical target
Date: Tue, 17 Nov 2015 08:20:26 +0100 [thread overview]
Message-ID: <564AD53A.1070009@twiddle.net> (raw)
In-Reply-To: <1447731653-4861-1-git-send-email-mreitz@redhat.com>
On 11/17/2015 04:40 AM, Max Reitz wrote:
> - tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
> - cpu_T[0], cpu_regs[R_EDX]);
> + tcg_gen_op3_i64(INDEX_op_mul_i64, cpu_regs[s->vex_v],
> + cpu_T[0], cpu_regs[R_EDX]);
> + if (TCG_TARGET_HAS_muluh_i64) {
> + tcg_gen_op3_i64(INDEX_op_muluh_i64, cpu_regs[reg],
> + cpu_T[0], cpu_regs[R_EDX]);
> + } else {
> + gen_helper_muluh_i64(cpu_regs[reg],
> + cpu_T[0], cpu_regs[R_EDX]);
> + }
This is not the correct fix.
I do see the operand write order present in the pseudo-code of the intel
manual. So that part of the diagnosis is fine.
But the correct solution is to put the outputs of tcg_gen_mulu2 into
temporaries (cpu_T[0] and cpu_T[1]) and then afterward write back the results
into the architectual registers in the correct order.
r~
prev parent reply other threads:[~2015-11-17 7:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-17 3:40 [Qemu-devel] [PATCH] target-i386: Fix mulx for identical target Max Reitz
2015-11-17 7:20 ` Richard Henderson [this message]
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