From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60361) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zydye-0002rN-2W for qemu-devel@nongnu.org; Tue, 17 Nov 2015 05:59:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zydyd-0007C3-6q for qemu-devel@nongnu.org; Tue, 17 Nov 2015 05:59:08 -0500 References: <1447702479-6997-1-git-send-email-serge.fdrv@gmail.com> <1447702479-6997-2-git-send-email-serge.fdrv@gmail.com> From: Sergey Fedorov Message-ID: <564B0874.3050902@gmail.com> Date: Tue, 17 Nov 2015 13:59:00 +0300 MIME-Version: 1.0 In-Reply-To: <1447702479-6997-2-git-send-email-serge.fdrv@gmail.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org On 16.11.2015 22:34, Sergey Fedorov wrote: > Coprocessor access instructions are allowed inside IT block. > gen_helper_access_check_cp_reg() can raise an exceptions thus condexec > bits should be updated before. > > Signed-off-by: Sergey Fedorov > --- > target-arm/translate.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 4351854..f1f8129 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) > break; > } > > + gen_set_condexec(dc); Ah, there must be gen_set_condexec(s). > gen_set_pc_im(s, s->pc - 4); > tmpptr = tcg_const_ptr(ri); > tcg_syn = tcg_const_i32(syndrome);