[Qemu-devel] [PATCH 0/2] target-arm: Missed gen_set_condexec() in AA32 translation

[Qemu-devel] [PATCH 0/2] target-arm: Missed gen_set_condexec() in AA32 translation

[Sergey Fedorov]

Sergey Fedorov (2):
  target-arm: Update condexec before CP access check in AA32 translation
  target-arm: Update condexec before arch BP check in AA32 translation

 target-arm/translate.c | 2 ++
 1 file changed, 2 insertions(+)

-- 
1.9.1

[Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation

[Sergey Fedorov]

Coprocessor access instructions are allowed inside IT block.
gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
bits should be updated before.

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
 target-arm/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4351854..f1f8129 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
                 break;
             }
 
+            gen_set_condexec(dc);
             gen_set_pc_im(s, s->pc - 4);
             tmpptr = tcg_const_ptr(ri);
             tcg_syn = tcg_const_i32(syndrome);
-- 
1.9.1

Re: [Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation

[Sergey Fedorov]

On 16.11.2015 22:34, Sergey Fedorov wrote:
> Coprocessor access instructions are allowed inside IT block.
> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
> bits should be updated before.
>
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
>  target-arm/translate.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 4351854..f1f8129 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
>                  break;
>              }
>  
> +            gen_set_condexec(dc);

Ah, there must be gen_set_condexec(s).

>              gen_set_pc_im(s, s->pc - 4);
>              tmpptr = tcg_const_ptr(ri);
>              tcg_syn = tcg_const_i32(syndrome);

Re: [Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation

[Peter Maydell]

On 17 November 2015 at 10:59, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
> On 16.11.2015 22:34, Sergey Fedorov wrote:
>> Coprocessor access instructions are allowed inside IT block.
>> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
>> bits should be updated before.
>>
>> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
>> ---
>>  target-arm/translate.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/target-arm/translate.c b/target-arm/translate.c
>> index 4351854..f1f8129 100644
>> --- a/target-arm/translate.c
>> +++ b/target-arm/translate.c
>> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
>>                  break;
>>              }
>>
>> +            gen_set_condexec(dc);
>
> Ah, there must be gen_set_condexec(s).

Yep. Are you going to resend?

thanks
-- PMM

Re: [Qemu-devel] [PATCH 1/2] target-arm: Update condexec before CP access check in AA32 translation

[Sergey Fedorov]

On 17.11.2015 16:31, Peter Maydell wrote:
> On 17 November 2015 at 10:59, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
>> On 16.11.2015 22:34, Sergey Fedorov wrote:
>>> Coprocessor access instructions are allowed inside IT block.
>>> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
>>> bits should be updated before.
>>>
>>> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
>>> ---
>>>  target-arm/translate.c | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/target-arm/translate.c b/target-arm/translate.c
>>> index 4351854..f1f8129 100644
>>> --- a/target-arm/translate.c
>>> +++ b/target-arm/translate.c
>>> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
>>>                  break;
>>>              }
>>>
>>> +            gen_set_condexec(dc);
>> Ah, there must be gen_set_condexec(s).
> Yep. Are you going to resend?

I got sort of ahead of myself with the patch. Yes, I will resend it now.

Best,
Sergey

[Qemu-devel] [PATCH 2/2] target-arm: Update condexec before arch BP check in AA32 translation

[Sergey Fedorov]

Architectural breakpoint check could raise an exceptions, thus condexec
bits should be updated before calling gen_helper_check_breakpoints().

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
 target-arm/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index f1f8129..9e9f851 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11374,6 +11374,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
                 if (bp->pc == dc->pc) {
                     if (bp->flags & BP_CPU) {
+                        gen_set_condexec(dc);
                         gen_set_pc_im(dc, dc->pc);
                         gen_helper_check_breakpoints(cpu_env);
                         /* End the TB early; it's likely not going to be executed */
-- 
1.9.1