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From: Leon Alrae <leon.alrae@imgtec.com>
To: James Hogan <james.hogan@imgtec.com>
Cc: qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH] target-mips: Fix exceptions while UX=0
Date: Tue, 17 Nov 2015 16:09:24 +0000	[thread overview]
Message-ID: <564B5134.7010106@imgtec.com> (raw)
In-Reply-To: <1447690698-20276-1-git-send-email-james.hogan@imgtec.com>

On 16/11/15 16:18, James Hogan wrote:
> However when exceptions are taken outside of exception level,
> mips_cpu_do_interrupt() manipulates the env->hflags directly rather than
> using compute_hflags() to update them, and this code wasn't updated
> accordingly. As a result, when UX is cleared, MIPS_HFLAG_AWRAP is set,
> but it doesn't get cleared on entry back into kernel mode due to an
> exception. Kernel mode then cannot access the 64-bit segments resulting
> in a nested exception loop.

Indeed, thanks for the fix.

> 
> Fix by updating mips_cpu_do_interrupt() to clear the MIPS_HFLAG_WRAP
> flag when necessary, according to compute_hflags().
> 
> Fixes: 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit...")
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Leon Alrae <leon.alrae@imgtec.com>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> ---
> Note, compute_hflags() doesn't seem to take KX into account pre-r6,
> which seems wrong.

Why does it seem wrong? According to PRA, prior to R6 (excluding the
R5+EVA case which we don’t support) this special behaviour for data
references (i.e. sign-extension of the effective address when 64-bit
addressing is disabled) is only in User Mode.

> ---
>  target-mips/helper.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index b3fe816fecf8..0625f610a015 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -725,6 +725,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
>              env->CP0_Status |= (1 << CP0St_EXL);
>              if (env->insn_flags & ISA_MIPS3) {
>                  env->hflags |= MIPS_HFLAG_64;
> +                if (!(env->insn_flags & ISA_MIPS64R6) ||
> +                    env->CP0_Status & (1 << CP0St_KX)) {
> +                    env->hflags &= ~MIPS_HFLAG_AWRAP;
> +                }

Any reason you skipped set_error_EPC and enter_DEPC? The flag needs to
be cleared there as well I think.

Thanks,
Leon

>              }
>              env->hflags |= MIPS_HFLAG_CP0;
>              env->hflags &= ~(MIPS_HFLAG_KSU);
> 

  reply	other threads:[~2015-11-17 16:09 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-16 16:18 [Qemu-devel] [PATCH] target-mips: Fix exceptions while UX=0 James Hogan
2015-11-17 16:09 ` Leon Alrae [this message]
2015-11-17 16:59   ` James Hogan

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