* [Qemu-devel] [kvm-unit-test RFC] x86: Memory instructions test case
@ 2015-11-04 21:21 Eduardo Habkost
2015-11-05 3:32 ` Xiao Guangrong
2015-11-18 11:23 ` Paolo Bonzini
0 siblings, 2 replies; 3+ messages in thread
From: Eduardo Habkost @ 2015-11-04 21:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Paolo Bonzini, Xiao Guangrong, kvm, Richard Henderson
Quickly hacked test case for memory instructions (clflush, mfence,
sfence, lfence, clflushopt, clwb, pcommit), that simply checks for #UD
exceptions.
This was useful to test TCG handling of those instructions.
The "fake clwb" part will probably break once a new instruction use
those opcodes.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
config/config-x86-common.mak | 2 +
config/config-x86_64.mak | 2 +-
x86/memory.c | 88 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 91 insertions(+), 1 deletion(-)
create mode 100644 x86/memory.c
diff --git a/config/config-x86-common.mak b/config/config-x86-common.mak
index c2f9908..b89684d 100644
--- a/config/config-x86-common.mak
+++ b/config/config-x86-common.mak
@@ -108,6 +108,8 @@ $(TEST_DIR)/vmx.elf: $(cstart.o) $(TEST_DIR)/vmx.o $(TEST_DIR)/vmx_tests.o
$(TEST_DIR)/debug.elf: $(cstart.o) $(TEST_DIR)/debug.o
+$(TEST_DIR)/memory.elf: $(cstart.o) $(TEST_DIR)/memory.o
+
arch_clean:
$(RM) $(TEST_DIR)/*.o $(TEST_DIR)/*.flat $(TEST_DIR)/*.elf \
$(TEST_DIR)/.*.d lib/x86/.*.d
diff --git a/config/config-x86_64.mak b/config/config-x86_64.mak
index 7d4eb34..ec4bded 100644
--- a/config/config-x86_64.mak
+++ b/config/config-x86_64.mak
@@ -7,7 +7,7 @@ tests = $(TEST_DIR)/access.flat $(TEST_DIR)/apic.flat \
$(TEST_DIR)/emulator.flat $(TEST_DIR)/idt_test.flat \
$(TEST_DIR)/xsave.flat $(TEST_DIR)/rmap_chain.flat \
$(TEST_DIR)/pcid.flat $(TEST_DIR)/debug.flat \
- $(TEST_DIR)/ioapic.flat
+ $(TEST_DIR)/ioapic.flat $(TEST_DIR)/memory.flat
tests += $(TEST_DIR)/svm.flat
tests += $(TEST_DIR)/vmx.flat
tests += $(TEST_DIR)/tscdeadline_latency.flat
diff --git a/x86/memory.c b/x86/memory.c
new file mode 100644
index 0000000..cd1eb46
--- /dev/null
+++ b/x86/memory.c
@@ -0,0 +1,88 @@
+/*
+ * Test for x86 cache and memory instructions
+ *
+ * Copyright (c) 2015 Red Hat Inc
+ *
+ * Authors:
+ * Eduardo Habkost <ehabkost@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.
+ */
+
+#include "libcflat.h"
+#include "desc.h"
+#include "processor.h"
+
+static long target;
+static volatile int ud;
+static volatile int isize;
+
+static void handle_ud(struct ex_regs *regs)
+{
+ ud = 1;
+ regs->rip += isize;
+}
+
+int main(int ac, char **av)
+{
+ struct cpuid cpuid7, cpuid1;
+ int xfail;
+
+ setup_idt();
+ handle_exception(UD_VECTOR, handle_ud);
+
+ cpuid1 = cpuid(1);
+ cpuid7 = cpuid_indexed(7, 0);
+
+ /* 3-byte instructions: */
+ isize = 3;
+
+ xfail = !(cpuid1.d & (1U << 19)); /* CLFLUSH */
+ ud = 0;
+ asm volatile("clflush (%0)" : : "b" (&target));
+ report_xfail("clflush", xfail, ud == 0);
+
+ xfail = !(cpuid1.d & (1U << 25)); /* SSE */
+ ud = 0;
+ asm volatile("sfence");
+ report_xfail("sfence", xfail, ud == 0);
+
+ xfail = !(cpuid1.d & (1U << 26)); /* SSE2 */
+ ud = 0;
+ asm volatile("lfence");
+ report_xfail("lfence", xfail, ud == 0);
+
+ ud = 0;
+ asm volatile("mfence");
+ report_xfail("mfence", xfail, ud == 0);
+
+ /* 4-byte instructions: */
+ isize = 4;
+
+ xfail = !(cpuid7.b & (1U << 23)); /* CLFLUSHOPT */
+ ud = 0;
+ /* clflushopt (%rbx): */
+ asm volatile(".byte 0x66, 0x0f, 0xae, 0x3b" : : "b" (&target));
+ report_xfail("clflushopt", xfail, ud == 0);
+
+ xfail = !(cpuid7.b & (1U << 24)); /* CLWB */
+ ud = 0;
+ /* clwb (%rbx): */
+ asm volatile(".byte 0x66, 0x0f, 0xae, 0x33" : : "b" (&target));
+ report_xfail("clwb", xfail, ud == 0);
+
+ ud = 0;
+ /* clwb requires a memory operand, the following is NOT a valid
+ * CLWB instruction (modrm == 0xF0).
+ */
+ asm volatile(".byte 0x66, 0x0f, 0xae, 0xf0");
+ report("fake clwb", ud);
+
+ xfail = !(cpuid7.b & (1U << 22)); /* PCOMMIT */
+ ud = 0;
+ /* pcommit: */
+ asm volatile(".byte 0x66, 0x0f, 0xae, 0xf8");
+ report_xfail("pcommit", xfail, ud == 0);
+
+ return report_summary();
+}
--
2.1.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [kvm-unit-test RFC] x86: Memory instructions test case
2015-11-04 21:21 [Qemu-devel] [kvm-unit-test RFC] x86: Memory instructions test case Eduardo Habkost
@ 2015-11-05 3:32 ` Xiao Guangrong
2015-11-18 11:23 ` Paolo Bonzini
1 sibling, 0 replies; 3+ messages in thread
From: Xiao Guangrong @ 2015-11-05 3:32 UTC (permalink / raw)
To: Eduardo Habkost, qemu-devel; +Cc: Paolo Bonzini, kvm, Richard Henderson
On 11/05/2015 05:21 AM, Eduardo Habkost wrote:
> Quickly hacked test case for memory instructions (clflush, mfence,
> sfence, lfence, clflushopt, clwb, pcommit), that simply checks for #UD
> exceptions.
>
> This was useful to test TCG handling of those instructions.
>
> The "fake clwb" part will probably break once a new instruction use
> those opcodes.
Tested it on the box on that these instruction are available, it worked.
Tested-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [kvm-unit-test RFC] x86: Memory instructions test case
2015-11-04 21:21 [Qemu-devel] [kvm-unit-test RFC] x86: Memory instructions test case Eduardo Habkost
2015-11-05 3:32 ` Xiao Guangrong
@ 2015-11-18 11:23 ` Paolo Bonzini
1 sibling, 0 replies; 3+ messages in thread
From: Paolo Bonzini @ 2015-11-18 11:23 UTC (permalink / raw)
To: Eduardo Habkost, qemu-devel; +Cc: Xiao Guangrong, kvm, Richard Henderson
On 04/11/2015 22:21, Eduardo Habkost wrote:
> Quickly hacked test case for memory instructions (clflush, mfence,
> sfence, lfence, clflushopt, clwb, pcommit), that simply checks for #UD
> exceptions.
>
> This was useful to test TCG handling of those instructions.
>
> The "fake clwb" part will probably break once a new instruction use
> those opcodes.
>
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> ---
> config/config-x86-common.mak | 2 +
> config/config-x86_64.mak | 2 +-
> x86/memory.c | 88 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 91 insertions(+), 1 deletion(-)
> create mode 100644 x86/memory.c
>
> diff --git a/config/config-x86-common.mak b/config/config-x86-common.mak
> index c2f9908..b89684d 100644
> --- a/config/config-x86-common.mak
> +++ b/config/config-x86-common.mak
> @@ -108,6 +108,8 @@ $(TEST_DIR)/vmx.elf: $(cstart.o) $(TEST_DIR)/vmx.o $(TEST_DIR)/vmx_tests.o
>
> $(TEST_DIR)/debug.elf: $(cstart.o) $(TEST_DIR)/debug.o
>
> +$(TEST_DIR)/memory.elf: $(cstart.o) $(TEST_DIR)/memory.o
> +
> arch_clean:
> $(RM) $(TEST_DIR)/*.o $(TEST_DIR)/*.flat $(TEST_DIR)/*.elf \
> $(TEST_DIR)/.*.d lib/x86/.*.d
> diff --git a/config/config-x86_64.mak b/config/config-x86_64.mak
> index 7d4eb34..ec4bded 100644
> --- a/config/config-x86_64.mak
> +++ b/config/config-x86_64.mak
> @@ -7,7 +7,7 @@ tests = $(TEST_DIR)/access.flat $(TEST_DIR)/apic.flat \
> $(TEST_DIR)/emulator.flat $(TEST_DIR)/idt_test.flat \
> $(TEST_DIR)/xsave.flat $(TEST_DIR)/rmap_chain.flat \
> $(TEST_DIR)/pcid.flat $(TEST_DIR)/debug.flat \
> - $(TEST_DIR)/ioapic.flat
> + $(TEST_DIR)/ioapic.flat $(TEST_DIR)/memory.flat
> tests += $(TEST_DIR)/svm.flat
> tests += $(TEST_DIR)/vmx.flat
> tests += $(TEST_DIR)/tscdeadline_latency.flat
> diff --git a/x86/memory.c b/x86/memory.c
> new file mode 100644
> index 0000000..cd1eb46
> --- /dev/null
> +++ b/x86/memory.c
> @@ -0,0 +1,88 @@
> +/*
> + * Test for x86 cache and memory instructions
> + *
> + * Copyright (c) 2015 Red Hat Inc
> + *
> + * Authors:
> + * Eduardo Habkost <ehabkost@redhat.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2.
> + */
> +
> +#include "libcflat.h"
> +#include "desc.h"
> +#include "processor.h"
> +
> +static long target;
> +static volatile int ud;
> +static volatile int isize;
> +
> +static void handle_ud(struct ex_regs *regs)
> +{
> + ud = 1;
> + regs->rip += isize;
> +}
> +
> +int main(int ac, char **av)
> +{
> + struct cpuid cpuid7, cpuid1;
> + int xfail;
> +
> + setup_idt();
> + handle_exception(UD_VECTOR, handle_ud);
> +
> + cpuid1 = cpuid(1);
> + cpuid7 = cpuid_indexed(7, 0);
> +
> + /* 3-byte instructions: */
> + isize = 3;
> +
> + xfail = !(cpuid1.d & (1U << 19)); /* CLFLUSH */
> + ud = 0;
> + asm volatile("clflush (%0)" : : "b" (&target));
> + report_xfail("clflush", xfail, ud == 0);
> +
> + xfail = !(cpuid1.d & (1U << 25)); /* SSE */
> + ud = 0;
> + asm volatile("sfence");
> + report_xfail("sfence", xfail, ud == 0);
> +
> + xfail = !(cpuid1.d & (1U << 26)); /* SSE2 */
> + ud = 0;
> + asm volatile("lfence");
> + report_xfail("lfence", xfail, ud == 0);
> +
> + ud = 0;
> + asm volatile("mfence");
> + report_xfail("mfence", xfail, ud == 0);
> +
> + /* 4-byte instructions: */
> + isize = 4;
> +
> + xfail = !(cpuid7.b & (1U << 23)); /* CLFLUSHOPT */
> + ud = 0;
> + /* clflushopt (%rbx): */
> + asm volatile(".byte 0x66, 0x0f, 0xae, 0x3b" : : "b" (&target));
> + report_xfail("clflushopt", xfail, ud == 0);
> +
> + xfail = !(cpuid7.b & (1U << 24)); /* CLWB */
> + ud = 0;
> + /* clwb (%rbx): */
> + asm volatile(".byte 0x66, 0x0f, 0xae, 0x33" : : "b" (&target));
> + report_xfail("clwb", xfail, ud == 0);
> +
> + ud = 0;
> + /* clwb requires a memory operand, the following is NOT a valid
> + * CLWB instruction (modrm == 0xF0).
> + */
> + asm volatile(".byte 0x66, 0x0f, 0xae, 0xf0");
> + report("fake clwb", ud);
> +
> + xfail = !(cpuid7.b & (1U << 22)); /* PCOMMIT */
> + ud = 0;
> + /* pcommit: */
> + asm volatile(".byte 0x66, 0x0f, 0xae, 0xf8");
> + report_xfail("pcommit", xfail, ud == 0);
> +
> + return report_summary();
> +}
>
Applied, thanks.
Paolo
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-11-18 11:23 ` Paolo Bonzini
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