From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a4bJR-0000mq-S9 for qemu-devel@nongnu.org; Thu, 03 Dec 2015 16:21:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a4bJM-0005J3-W2 for qemu-devel@nongnu.org; Thu, 03 Dec 2015 16:21:13 -0500 Sender: Richard Henderson References: <1448922238-5696-1-git-send-email-Andrew.Baumann@microsoft.com> From: Richard Henderson Message-ID: <5660B23F.9030701@twiddle.net> Date: Thu, 3 Dec 2015 13:21:03 -0800 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-arm: raise exception on misaligned LDREX operands List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Laurent Desnogues Cc: qemu-arm , QEMU Developers , Andrew Baumann On 12/03/2015 07:08 AM, Peter Maydell wrote: > On 3 December 2015 at 14:58, Laurent Desnogues > wrote: >> On Thu, Dec 3, 2015 at 3:36 PM, Peter Maydell wrote: >>> On 30 November 2015 at 22:23, Andrew Baumann >>> wrote: >>>> Qemu does not generally perform alignment checks. However, the ARM ARM >>>> requires implementation of alignment exceptions for a number of cases >>>> including LDREX, and Windows-on-ARM relies on this. > >>> TCG supports "this load/store should do an alignment check" >>> using the MO_ALIGN TCGMemOp flag (which results in a call to >>> the CPU's do_unaligned_access hook if the guest address is not >>> aligned). I think we should use this core-code functionality >>> rather than rolling our own equivalent (it is more efficient). >>> There are some examples in a few of the other targets (eg MIPS) >>> of how to do this, but basically you need to arrange that the >>> initial loads in gen_load_exclusive get the MO_ALIGN flag >>> ORed in, and then wire up the do_unaligned_access hook and >>> make it raise a suitable exception. >> >> After quickly looking at the code in softmmu_template.h, I wonder if >> MO_ALIGN would correcly handle the ldrexd pair case which requires an >> 8-byte alignment but does 2 4-byte loads (even if the code is tweaked >> to read 8-byte at once, then checking 16-byte alignment of AArch64 >> ldxp 64-bit could not be handled correctly). > > You're right, those are not going to be handled correctly. > But I think it would be better to enhance the MO_ALIGN > handling somehow to deal with "must be more highly aligned than > the datasize" cases as well as the "alignment must match datasize" > ones. What's the full set of features that you'd like here? > (As you say we'd need > to do the ldrexd as a 64-bit access, but we should do that > anyway because it's supposed to be single-copy-atomic, > architecturally speaking.) Something to remember for future is that we're not doing single-copy of 64-bit data for 32-bit hosts. I'm not even sure that's generally possible without generating awful code. r~