From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8PVe-0004sm-Sa for qemu-devel@nongnu.org; Mon, 14 Dec 2015 04:33:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a8PVb-0005o4-LR for qemu-devel@nongnu.org; Mon, 14 Dec 2015 04:33:34 -0500 Received: from mx1.redhat.com ([209.132.183.28]:34404) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8PVb-0005o0-GU for qemu-devel@nongnu.org; Mon, 14 Dec 2015 04:33:31 -0500 References: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> From: Paolo Bonzini Message-ID: <566E8CE3.2040104@redhat.com> Date: Mon, 14 Dec 2015 10:33:23 +0100 MIME-Version: 1.0 In-Reply-To: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alvise Rigo , qemu-devel@nongnu.org, mttcg@greensocs.com Cc: claudio.fontana@huawei.com, "Emilio G. Cota" , jani.kokkonen@huawei.com, tech@virtualopensystems.com, alex.bennee@linaro.org, rth@twiddle.net On 14/12/2015 09:41, Alvise Rigo wrote: > In theory, the provided implementation of TCG LoadLink/StoreConditional > can be used to properly handle atomic instructions on any architecture. No, _in theory_ this implementation is wrong. If a normal store can make a concurrent LL-SC pair fail, it's provably _impossible_ to handle LL/SC with a wait-free fast path for normal stores. If we decide that it's "good enough", because the race is incredibly rare and doesn't happen anyway for spinlocks, then fine. But it should be represented correctly in the commit messages. Paolo