From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a97oK-0007m2-Ka for qemu-devel@nongnu.org; Wed, 16 Dec 2015 03:51:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a97oH-0000fh-EN for qemu-devel@nongnu.org; Wed, 16 Dec 2015 03:51:48 -0500 Received: from mail-wm0-x232.google.com ([2a00:1450:400c:c09::232]:38243) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a97oH-0000fd-8a for qemu-devel@nongnu.org; Wed, 16 Dec 2015 03:51:45 -0500 Received: by mail-wm0-x232.google.com with SMTP id l126so28123550wml.1 for ; Wed, 16 Dec 2015 00:51:45 -0800 (PST) Sender: Paolo Bonzini References: <1449926146-14828-1-git-send-email-arei.gonglei@huawei.com> <566E9259.2010404@redhat.com> <33183CC9F5247A488A2544077AF19020B02B4533@SZXEMA503-MBS.china.huawei.com> <566EBB34.5030205@redhat.com> <33183CC9F5247A488A2544077AF19020B02B45BB@SZXEMA503-MBS.china.huawei.com> <566EC61A.7090407@redhat.com> <33183CC9F5247A488A2544077AF19020B02B4BE3@SZXEMA503-MBS.china.huawei.com> <145192308.40660604.1450176186593.JavaMail.zimbra@redhat.com> <20151215185335.GF17283@potion.brq.redhat.com> From: Paolo Bonzini Message-ID: <5671261F.4010305@redhat.com> Date: Wed, 16 Dec 2015 09:51:43 +0100 MIME-Version: 1.0 In-Reply-To: <20151215185335.GF17283@potion.brq.redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] rtc: introduce nmi disable bit handler for cmos List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Radim Krcmar Cc: ehabkost@redhat.com, "Huangpeng (Peter)" , qemu-devel@nongnu.org, "Gonglei (Arei)" , kevin@koconnor.net, rth@twiddle.net On 15/12/2015 19:53, Radim Krcmar wrote: > 2015-12-15 05:43-0500, Paolo Bonzini: >>> Hi Paolo, >>> >>> /* for KVM_GET/SET_VCPU_EVENTS */ >>> struct kvm_vcpu_events { >>> ... >>> struct { >>> __u8 injected; >>> __u8 pending; >>> __u8 masked; >>> __u8 pad; >>> } nmi; >>> ... >>> >>> I found that the nmi.masked property does these enable or disable NMI jobs. >>> So, I think we don't need to add a new bit. Right? >> >> nmi.masked says whether the CPU is accepting the NMIs, and is cleared >> by the next IRET instruction. This is a different thing; it probably >> shouldn't affect NMI IPIs, and it definitely should remain set until >> cleared via the RTC. So it should be something like >> >> _u8 external_nmi_disabled; >> >> or similar. >> >> *However* I found this in the ICH9 datasheet: >> >> The ICH9's I/O APIC can only send interrupts due to interrupts which >> do not include SMI, NMI or INIT. This means that in IA-32/Intel ® 64 >> based platforms, Front Side Bus interrupt message format delivery modes >> 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, >> must not be used and is not supported. >> >> In theory the PIIX4 could deliver such messages, but perhaps we could >> disable them in the KVM IOAPIC. If we do this, there is no need for a >> change to struct kvm_vcpu_events, because all external NMI sources will >> be in userspace. >> >> Radim, what do you think? > > I looked at the 440fx, piix, and 82083aa(ioapic) datasheets and the > NMI_EN bit doesn't seem to be propagated into the IOAPIC. > The IOAPIC datasheet doesn't mention a thing about NMI masking and PIIX4 > generates NMI on SERR# or IOCHK# so it seems that the NMI_EN feature > only changes the behavior of those two ... > > I think it's best to do nothing in KVM. Then Gonglei's patch (apart from the issues that Eduardo pointed out) is fine. Paolo