* [PATCH RFC 1/3] target/arm: Implement SVE2 AESMC, AESIMC
2020-04-23 22:37 [PATCH RFC 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
@ 2020-04-23 22:37 ` Stephen Long
2020-04-24 21:41 ` Richard Henderson
2020-04-23 22:37 ` [PATCH RFC 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
2020-04-23 22:37 ` [PATCH RFC 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1 Stephen Long
2 siblings, 1 reply; 5+ messages in thread
From: Stephen Long @ 2020-04-23 22:37 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/helper-sve.h | 3 +++
target/arm/sve.decode | 10 ++++++++++
target/arm/sve_helper.c | 13 +++++++++++++
target/arm/translate-sve.c | 18 ++++++++++++++++++
4 files changed, 44 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index f6ae814021..6e8421991c 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2687,3 +2687,6 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(sve2_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 3a2a4a7f1c..a83420e690 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -92,6 +92,10 @@
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
+# One operand with unused vector element size
+@rdn_e0 ........ .. ........... . ..... rd:5 \
+ &rr_esz rn=%reg_movprfx esz=0
+
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
@@ -1387,3 +1391,9 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm
CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx
SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
+
+#### SVE2 Crypto Extensions
+
+## SVE2 crypto unary operations
+AESMC 01000101 00 10000011100 0 00000 ..... @rdn_e0
+AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 55e2c32f03..f25bb5338d 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7428,3 +7428,16 @@ void HELPER(sve2_xar_s)(void *vd, void *vn, void *vm, uint32_t desc)
d[i] = ror32(n[i] ^ m[i], shr);
}
}
+
+#define DO_CRYPTO_AESMC(NAME, DECRYPT) \
+void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
+{ \
+ intptr_t i, opr_sz = simd_oprsz(desc); \
+ void *d = vd, *n = vn; \
+ for (i = 0; i < opr_sz; i += 16) { \
+ HELPER(crypto_aesmc)(vd + i, vn + i, DECRYPT); \
+ }
+}
+
+DO_CRYPTO_AESMC(sve2_aesmc, 0);
+DO_CRYPTO_AESMC(sve2_aesimc, 1);
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 20eb588cb3..03463308ca 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7882,3 +7882,21 @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
};
return do_sve2_zzzz_fn(s, a->rd, a->rn, a->rm, a->ra, fns[a->esz], a->rot);
}
+
+#define DO_SVE2_AES_CRYPTO(NAME, name) \
+static bool trans_##NAME(DisasContext *s, arg_rr_esz *a) \
+{ \
+ if (!dc_isar_feature(aa64_sve2_aes, s)) { \
+ return false; \
+ } \
+ if (sve_access_check(s)) { \
+ unsigned vsz = vec_full_reg_size(s); \
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd), \
+ vec_full_reg_offset(s, a->rn), \
+ vsz, vsz, 0, gen_helper_sve2_##name); \
+ } \
+ return true; \
+}
+
+DO_SVE2_AES_CRYPTO(AESMC, aesmc)
+DO_SVE2_AES_CRYPTO(AESIMC, aesimc)
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH RFC 1/3] target/arm: Implement SVE2 AESMC, AESIMC
2020-04-23 22:37 ` [PATCH RFC 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
@ 2020-04-24 21:41 ` Richard Henderson
0 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2020-04-24 21:41 UTC (permalink / raw)
To: Stephen Long, qemu-devel; +Cc: qemu-arm, apazos
On 4/23/20 3:37 PM, Stephen Long wrote:
> +#define DO_CRYPTO_AESMC(NAME, DECRYPT) \
> +void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
> +{ \
> + intptr_t i, opr_sz = simd_oprsz(desc); \
> + void *d = vd, *n = vn; \
> + for (i = 0; i < opr_sz; i += 16) { \
> + HELPER(crypto_aesmc)(vd + i, vn + i, DECRYPT); \
> + }
> +}
Better, IMO, is to add a "desc" parameter to crypto_aesmc and move the loop
there. Then all variants of this operation use the exact same helper. The
separate decrypt parameter would become simd_data().
Same for the other two patches in this series.
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH RFC 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E
2020-04-23 22:37 [PATCH RFC 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-23 22:37 ` [PATCH RFC 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
@ 2020-04-23 22:37 ` Stephen Long
2020-04-23 22:37 ` [PATCH RFC 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1 Stephen Long
2 siblings, 0 replies; 5+ messages in thread
From: Stephen Long @ 2020-04-23 22:37 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/cpu.h | 5 +++++
target/arm/helper-sve.h | 4 ++++
target/arm/sve.decode | 6 ++++++
target/arm/sve_helper.c | 25 +++++++++++++++++++++++++
target/arm/translate-sve.c | 16 ++++++++++++++++
5 files changed, 56 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b7c7946771..4dda0cf6c1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3870,6 +3870,11 @@ static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
}
+static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 6e8421991c..3da9590da5 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2690,3 +2690,7 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_3(sve2_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(sve2_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a83420e690..4bbf219cb6 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -98,6 +98,7 @@
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
+@pd5_pn5_e0 ........ ........ ...... rn:5 rd:5 &rr_esz esz=0
# Two operand
@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
@@ -1397,3 +1398,8 @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
## SVE2 crypto unary operations
AESMC 01000101 00 10000011100 0 00000 ..... @rdn_e0
AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
+
+## SVE2 crpyto destructive binary operations
+AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
+AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
+SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index f25bb5338d..0581f33fc7 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7441,3 +7441,28 @@ void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
DO_CRYPTO_AESMC(sve2_aesmc, 0);
DO_CRYPTO_AESMC(sve2_aesimc, 1);
+
+#define DO_CRYPTO_AESE(NAME, DECRYPT) \
+void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
+{ \
+ intptr_t i, opr_sz = simd_oprsz(desc); \
+ void *d = vd, *n = vn; \
+ for (i = 0; i < opr_sz; i += 16) { \
+ HELPER(crypto_aese)(vd + i, vn + i, DECRYPT); \
+ }
+}
+
+DO_CRYPTO_AESE(sve2_aese, 0);
+DO_CRYPTO_AESE(sve2_aesd, 1);
+
+#undef DO_CRYPTO_AESE
+#undef DO_CRYPTO_AESMC
+
+void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ void *d = vd, *n = vn;
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4e)(vd + i, vn + i);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 03463308ca..d991dcdb1c 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7900,3 +7900,19 @@ static bool trans_##NAME(DisasContext *s, arg_rr_esz *a) \
DO_SVE2_AES_CRYPTO(AESMC, aesmc)
DO_SVE2_AES_CRYPTO(AESIMC, aesimc)
+DO_SVE2_AES_CRYPTO(AESE, aese)
+DO_SVE2_AES_CRYPTO(AESD, aesd)
+
+static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vsz, vsz, 0, gen_helper_sve2_sm4e);
+ }
+ return true;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH RFC 3/3] target/arm: Implement SVE2 SM4EKEY, RAX1
2020-04-23 22:37 [PATCH RFC 0/3] target/arm: Implement SVE2 Crypto Extensions Stephen Long
2020-04-23 22:37 ` [PATCH RFC 1/3] target/arm: Implement SVE2 AESMC, AESIMC Stephen Long
2020-04-23 22:37 ` [PATCH RFC 2/3] target/arm: Implement SVE2 AESE, AESD, SM4E Stephen Long
@ 2020-04-23 22:37 ` Stephen Long
2 siblings, 0 replies; 5+ messages in thread
From: Stephen Long @ 2020-04-23 22:37 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm, richard.henderson, apazos
Signed-off-by: Stephen Long <steplong@quicinc.com>
---
target/arm/helper-sve.h | 3 +++
target/arm/sve.decode | 4 ++++
target/arm/sve_helper.c | 21 +++++++++++++++++++++
target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 3da9590da5..07681728ba 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2694,3 +2694,6 @@ DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(sve2_sm4ekey, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(sve2_rax1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 4bbf219cb6..1e98c6aa2f 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -1403,3 +1403,7 @@ AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
+
+## SVE2 crypto constructive binary operations
+SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
+RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 0581f33fc7..e8299b33ee 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7466,3 +7466,24 @@ void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
HELPER(crypto_sm4e)(vd + i, vn + i);
}
}
+
+void HELPER(sve2_sm4ekey)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ void *d = vd, *n = vn;
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4ekey)(vd + i, vn + i, vm + i);
+ }
+}
+
+void HELPER(sve2_rax1)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm;
+
+ for (i = 0; i < opr_sz; ++i) {
+ uint64_t nn = n[i];
+ uint64_t mm = m[i];
+ d[i] = nn ^ rol64(mm, 1);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d991dcdb1c..671f09efa7 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7916,3 +7916,33 @@ static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
}
return true;
}
+
+static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_sve2_sm4ekey);
+ }
+ return true;
+}
+
+static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vec_full_reg_offset(s, a->rm),
+ vsz, vsz, 0, gen_helper_sve2_rax1);
+ }
+ return true;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread