From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35897) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGZdm-000287-RJ for qemu-devel@nongnu.org; Tue, 05 Jan 2016 16:59:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aGZdi-00080o-M5 for qemu-devel@nongnu.org; Tue, 05 Jan 2016 16:59:42 -0500 Received: from mx1.redhat.com ([209.132.183.28]:59564) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGZdi-00080k-CY for qemu-devel@nongnu.org; Tue, 05 Jan 2016 16:59:38 -0500 References: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> <1451376295-28834-10-git-send-email-hpoussin@reactos.org> From: John Snow Message-ID: <568C3CC8.40903@redhat.com> Date: Tue, 5 Jan 2016 16:59:36 -0500 MIME-Version: 1.0 In-Reply-To: <1451376295-28834-10-git-send-email-hpoussin@reactos.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 09/17] i8257: implement the IsaDma interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Herv=c3=a9_Poussineau?= , qemu-devel@nongnu.org Cc: Paolo Bonzini , "Michael S. Tsirkin" Accidental duplicate send of patch #09 with minor differences in the commit message... Assuming this one is the "correct" one and just discarding the other. On 12/29/2015 03:04 AM, Herv=C3=A9 Poussineau wrote: > Rewrite the global DMA_*() functions to use the IsaDma interface. > Note that these functions will be deleted in a few commits. >=20 > Signed-off-by: Herv=C3=A9 Poussineau > --- > hw/dma/i8257.c | 148 +++++++++++++++++++++++++++++++++++++++++++++----= -------- > 1 file changed, 117 insertions(+), 31 deletions(-) >=20 > diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c > index 20231d6..cf4b0a7 100644 > --- a/hw/dma/i8257.c > +++ b/hw/dma/i8257.c > @@ -77,8 +77,6 @@ typedef struct I8257State { > int running; > } I8257State; > =20 > -static I8257State *dma_controllers[2]; > - > enum { > CMD_MEMORY_TO_MEMORY =3D 0x01, > CMD_FIXED_ADDRESS =3D 0x02, > @@ -321,31 +319,36 @@ static uint64_t i8257_read_cont(void *opaque, hwa= ddr nport, unsigned size) > return val; > } > =20 > -int DMA_get_channel_mode (int nchan) > +static IsaDmaTransferMode i8257_dma_get_transfer_mode(IsaDma *obj, int= nchan) > +{ > + I8257State *d =3D I8257(obj); > + return (d->regs[nchan & 3].mode >> 2) & 3; > +} > + > +static bool i8257_dma_has_autoinitialization(IsaDma *obj, int nchan) > { > - return dma_controllers[nchan > 3]->regs[nchan & 3].mode; > + I8257State *d =3D I8257(obj); > + return (d->regs[nchan & 3].mode >> 4) & 1; > } > =20 > -void DMA_hold_DREQ (int nchan) > +static void i8257_dma_hold_DREQ(IsaDma *obj, int nchan) > { > - int ncont, ichan; > + I8257State *d =3D I8257(obj); > + int ichan; > =20 > - ncont =3D nchan > 3; > ichan =3D nchan & 3; > - linfo ("held cont=3D%d chan=3D%d\n", ncont, ichan); > - dma_controllers[ncont]->status |=3D 1 << (ichan + 4); > - i8257_dma_run(dma_controllers[ncont]); > + d->status |=3D 1 << (ichan + 4); > + i8257_dma_run(d); > } > =20 > -void DMA_release_DREQ (int nchan) > +static void i8257_dma_release_DREQ(IsaDma *obj, int nchan) > { > - int ncont, ichan; > + I8257State *d =3D I8257(obj); > + int ichan; > =20 > - ncont =3D nchan > 3; > ichan =3D nchan & 3; > - linfo ("released cont=3D%d chan=3D%d\n", ncont, ichan); > - dma_controllers[ncont]->status &=3D ~(1 << (ichan + 4)); > - i8257_dma_run(dma_controllers[ncont]); > + d->status &=3D ~(1 << (ichan + 4)); > + i8257_dma_run(d); > } > =20 > static void i8257_channel_run(I8257State *d, int ichan) > @@ -405,24 +408,26 @@ out: > } > } > =20 > -void DMA_register_channel (int nchan, > - DMA_transfer_handler transfer_handler, > - void *opaque) > +static void i8257_dma_register_channel(IsaDma *obj, int nchan, > + DMA_transfer_handler transfer_h= andler, > + void *opaque) > { > + I8257State *d =3D I8257(obj); > struct dma_regs *r; > - int ichan, ncont; > + int ichan; > =20 > - ncont =3D nchan > 3; > ichan =3D nchan & 3; > =20 > - r =3D dma_controllers[ncont]->regs + ichan; > + r =3D d->regs + ichan; > r->transfer_handler =3D transfer_handler; > r->opaque =3D opaque; > } > =20 > -int DMA_read_memory (int nchan, void *buf, int pos, int len) > +static int i8257_dma_read_memory(IsaDma *obj, int nchan, void *buf, in= t pos, > + int len) > { > - struct dma_regs *r =3D &dma_controllers[nchan > 3]->regs[nchan & 3= ]; > + I8257State *d =3D I8257(obj); > + struct dma_regs *r =3D &d->regs[nchan & 3]; > hwaddr addr =3D ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->n= ow[ADDR]; > =20 > if (r->mode & 0x20) { > @@ -442,9 +447,11 @@ int DMA_read_memory (int nchan, void *buf, int pos= , int len) > return len; > } > =20 > -int DMA_write_memory (int nchan, void *buf, int pos, int len) > +static int i8257_dma_write_memory(IsaDma *obj, int nchan, void *buf, i= nt pos, > + int len) > { > - struct dma_regs *r =3D &dma_controllers[nchan > 3]->regs[nchan & 3= ]; > + I8257State *s =3D I8257(obj); > + struct dma_regs *r =3D &s->regs[nchan & 3]; > hwaddr addr =3D ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->n= ow[ADDR]; > =20 > if (r->mode & 0x20) { > @@ -467,10 +474,10 @@ int DMA_write_memory (int nchan, void *buf, int p= os, int len) > /* request the emulator to transfer a new DMA memory block ASAP (even > * if the idle bottom half would not have exited the iothread yet). > */ > -void DMA_schedule(void) > +static void i8257_dma_schedule(IsaDma *obj) > { > - if (dma_controllers[0]->dma_bh_scheduled || > - dma_controllers[1]->dma_bh_scheduled) { > + I8257State *d =3D I8257(obj); > + if (d->dma_bh_scheduled) { > qemu_notify_event(); > } > } > @@ -604,11 +611,85 @@ static Property i8257_properties[] =3D { > static void i8257_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > + IsaDmaClass *idc =3D ISADMA_CLASS(klass); > =20 > dc->realize =3D i8257_realize; > dc->reset =3D i8257_reset; > dc->vmsd =3D &vmstate_i8257; > dc->props =3D i8257_properties; > + > + idc->get_transfer_mode =3D i8257_dma_get_transfer_mode; > + idc->has_autoinitialization =3D i8257_dma_has_autoinitialization; > + idc->read_memory =3D i8257_dma_read_memory; > + idc->write_memory =3D i8257_dma_write_memory; > + idc->hold_DREQ =3D i8257_dma_hold_DREQ; > + idc->release_DREQ =3D i8257_dma_release_DREQ; > + idc->schedule =3D i8257_dma_schedule; > + idc->register_channel =3D i8257_dma_register_channel; > +} > + > +static ISABus *i8257_bus; > + > +int DMA_get_channel_mode(int nchan) > +{ > + IsaDma *dma =3D isa_get_dma(i8257_bus, nchan); > + IsaDmaClass *k =3D ISADMA_GET_CLASS(dma); > + uint8_t res =3D 0; > + > + res |=3D k->has_autoinitialization(dma, nchan) ? 0 : 0x10; > + res |=3D k->get_transfer_mode(dma, nchan) << 2; > + > + return res; > +} > + > +int DMA_read_memory(int nchan, void *buf, int pos, int size) > +{ > + IsaDma *dma =3D isa_get_dma(i8257_bus, nchan); > + IsaDmaClass *k =3D ISADMA_GET_CLASS(dma); > + return k->read_memory(dma, nchan, buf, pos, size); > +} > + > +int DMA_write_memory(int nchan, void *buf, int pos, int size) > +{ > + IsaDma *dma =3D isa_get_dma(i8257_bus, nchan); > + IsaDmaClass *k =3D ISADMA_GET_CLASS(dma); > + return k->write_memory(dma, nchan, buf, pos, size); > +} > + > +void DMA_hold_DREQ(int nchan) > +{ > + IsaDma *dma =3D isa_get_dma(i8257_bus, nchan); > + IsaDmaClass *k =3D ISADMA_GET_CLASS(dma); > + k->hold_DREQ(dma, nchan); > +} > + > +void DMA_release_DREQ(int nchan) > +{ > + IsaDma *dma =3D isa_get_dma(i8257_bus, nchan); > + IsaDmaClass *k =3D ISADMA_GET_CLASS(dma); > + k->release_DREQ(dma, nchan); > +} > + > +void DMA_schedule(void) > +{ > + IsaDma *dma; > + IsaDmaClass *k; > + int i; > + > + for (i =3D 0; i < 2; i++) { > + dma =3D isa_get_dma(i8257_bus, i << 2); > + k =3D ISADMA_GET_CLASS(dma); > + k->schedule(dma); > + } > +} > + > +void DMA_register_channel(int nchan, > + DMA_transfer_handler transfer_handler, > + void *opaque) > +{ > + IsaDma *dma =3D isa_get_dma(i8257_bus, nchan); > + IsaDmaClass *k =3D ISADMA_GET_CLASS(dma); > + k->register_channel(dma, nchan, transfer_handler, opaque); > } > =20 > static const TypeInfo i8257_info =3D { > @@ -616,6 +697,10 @@ static const TypeInfo i8257_info =3D { > .parent =3D TYPE_ISA_DEVICE, > .instance_size =3D sizeof(I8257State), > .class_init =3D i8257_class_init, > + .interfaces =3D (InterfaceInfo[]) { > + { TYPE_ISADMA }, > + { } > + } > }; > =20 > static void i8257_register_types(void) > @@ -637,7 +722,6 @@ void DMA_init(ISABus *bus, int high_page_enable) > qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1= ); > qdev_prop_set_int32(d, "dshift", 0); > qdev_init_nofail(d); > - dma_controllers[0] =3D I8257(d); > =20 > isa2 =3D isa_create(bus, TYPE_I8257); > d =3D DEVICE(isa2); > @@ -646,5 +730,7 @@ void DMA_init(ISABus *bus, int high_page_enable) > qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1= ); > qdev_prop_set_int32(d, "dshift", 1); > qdev_init_nofail(d); > - dma_controllers[1] =3D I8257(d); > + > + isa_bus_dma(bus, ISADMA(isa1), ISADMA(isa2)); > + i8257_bus =3D bus; > } >=20