From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60630) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHE4r-00017X-Tz for qemu-devel@nongnu.org; Thu, 07 Jan 2016 12:10:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aHE4n-0006sI-HA for qemu-devel@nongnu.org; Thu, 07 Jan 2016 12:10:21 -0500 Received: from bh-25.webhostbox.net ([208.91.199.152]:44346) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHE4n-0006rc-BS for qemu-devel@nongnu.org; Thu, 07 Jan 2016 12:10:17 -0500 References: <567B41E3.5060800@roeck-us.net> <20160107155310.GA4064@red-moon> <20160107163722.GB4064@red-moon> From: Guenter Roeck Message-ID: <568E9BF6.6020809@roeck-us.net> Date: Thu, 7 Jan 2016 09:10:14 -0800 MIME-Version: 1.0 In-Reply-To: <20160107163722.GB4064@red-moon> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] arm64 qemu tests failing in linux-next since 'arm64: kernel: enforce pmuserenr_el0 initialization and restore' List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Lorenzo Pieralisi , Peter Maydell Cc: Mark Rutland , Will Deacon , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , QEMU Developers On 01/07/2016 08:37 AM, Lorenzo Pieralisi wrote: > On Thu, Jan 07, 2016 at 03:58:15PM +0000, Peter Maydell wrote: >> On 7 January 2016 at 15:53, Lorenzo Pieralisi wrote: >>> On Thu, Jan 07, 2016 at 01:25:35PM +0000, Peter Maydell wrote: >>>> We had previously been relying on the kernel not attempting to >>>> touch the PMU if the ID_AA64DFR0_EL1 PMUVer bits read 0000 >>>> ("Performance Monitors extension System registers not implemented"). >>> >>> Ok, thanks for looking into this. I wonder why reading pmcr_el0 does >>> not suffer from the same problem though. >> >> Just a pragmatic thing on QEMU's end, I expect -- the kernel already >> touched PMCR_EL0 and we wanted to be able to boot it, so we have an >> implementation of it. > > If that's the case, that was the wrong approach IMHO. QEMU has to comply > with the Aarch64 architecture which means that either the CPU it models > has a Performance Monitors extension or it does not. If reading pmcr_el0 > does not fault I could tell you this is a QEMU regression because currently > it _does_ model pmcr_el0 while (hopefully) ID_AA64DFR0_EL1 PMUVer reports > it should not. > Strictly speaking you may be right (regression is a bit strong, though), but for my part I tend to be pragmatic. A warning message such as "Access to unimplemented register X" may be useful, but effectively disabling all (older) aarch64 Linux kernels in qemu could be seen as a bit dogmatic and would not be very helpful. > I will add code that guards both register accesses to fix both bugs at > once. > I assume you'll fix the the unconditional access(es) to pmcr_el0. Question here is the scope of registers associated with PMUVer. Are there any other registers which would need to be guarded ? Thanks, Guenter