From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48750) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHO9s-000669-Gh for qemu-devel@nongnu.org; Thu, 07 Jan 2016 22:56:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aHO9q-0008I3-Bi for qemu-devel@nongnu.org; Thu, 07 Jan 2016 22:56:12 -0500 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:35304) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHO9p-0008Fp-39 for qemu-devel@nongnu.org; Thu, 07 Jan 2016 22:56:10 -0500 Received: by mail-pa0-x22b.google.com with SMTP id ho8so14003714pac.2 for ; Thu, 07 Jan 2016 19:56:08 -0800 (PST) References: <1450665670-18323-1-git-send-email-david@gibson.dropbear.id.au> <1450665670-18323-3-git-send-email-david@gibson.dropbear.id.au> From: Alexey Kardashevskiy Message-ID: <568F3352.9090306@ozlabs.ru> Date: Fri, 8 Jan 2016 14:56:02 +1100 MIME-Version: 1.0 In-Reply-To: <1450665670-18323-3-git-send-email-david@gibson.dropbear.id.au> Content-Type: text/plain; charset=koi8-r; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , benh@kernel.crashing.org, mdroth@linux.vnet.ibm.com Cc: lvivier@redhat.com, thuth@redhat.com, qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org On 12/21/2015 01:41 PM, David Gibson wrote: > Now that the spapr code has been extended to support 64kiB pages, we can > allow guests to use 64kiB pages on an emulated POWER8 by adding it to the > "segment_page_sizes" structure which is advertised via the device tree. > > For now we just add support for 64kiB pages in 64kiB page segments. Real > POWER8 also supports 64kiB pages in 4kiB page segments, but that will > require more work to implement. > > Real POWER7s (and maybe some other CPU models) also support 64kiB pages, > however, I don't want to add support there without double checking if they > use the same HPTE and SLB encodings (in principle these are implementation > dependent). > > Signed-off-by: David Gibson > --- > target-ppc/translate_init.c | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index e88dc7f..ae5a269 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > { > DeviceClass *dc = DEVICE_CLASS(oc); > PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); > + static const struct ppc_segment_page_sizes POWER8_sps = { > + .sps = { > + { .page_shift = 12, /* 4K */ > + .slb_enc = 0, > + .enc = { { .page_shift = 12, .pte_enc = 0 } } > + }, > + { .page_shift = 16, /* 64K */ > + .slb_enc = 0x110, > + .enc = { { .page_shift = 16, .pte_enc = 0x1 } } > + }, > + { .page_shift = 24, /* 16M */ > + .slb_enc = 0x100, > + .enc = { { .page_shift = 24, .pte_enc = 0 } } > + }, > + } > + }; In order to educate myself - where did 0x110/0x100 come from? Is not 0x110 SLB_VSID_64K (which does not use SLB_VSID_L by accident?)? And is 0x100 SLB_VSID_L? I just wanted to double check if POWER7 uses the same encoding and it is not that simple to trace what came from where... > > dc->fw_name = "PowerPC,POWER8"; > dc->desc = "POWER8"; > @@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) > pcc->l1_dcache_size = 0x8000; > pcc->l1_icache_size = 0x8000; > pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; > + pcc->sps = &POWER8_sps; > } > #endif /* defined (TARGET_PPC64) */ > > -- Alexey