From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHY7a-000097-Mk for qemu-devel@nongnu.org; Fri, 08 Jan 2016 09:34:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aHY7X-0007dR-Fb for qemu-devel@nongnu.org; Fri, 08 Jan 2016 09:34:30 -0500 Received: from s16892447.onlinehome-server.info ([82.165.15.123]:41030) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHY7X-0007dL-9v for qemu-devel@nongnu.org; Fri, 08 Jan 2016 09:34:27 -0500 References: <1447437247-19512-1-git-send-email-mark.cave-ayland@ilande.co.uk> <1447437247-19512-2-git-send-email-mark.cave-ayland@ilande.co.uk> From: Mark Cave-Ayland Message-ID: <568FC8DB.7040308@ilande.co.uk> Date: Fri, 8 Jan 2016 14:34:03 +0000 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/3] sun4u: split out NPT and INT_DIS into separate CPUTimer fields List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers , Artyom Tarasenko On 08/01/16 14:05, Peter Maydell wrote: > On 13 November 2015 at 17:54, Mark Cave-Ayland > wrote: >> Currently there is confusion between use of these bits for the timer and timer >> compare registers (while they both have the same value, the behaviour is >> different). Split into two separate CPUTimer fields so we can always reference >> the correct value. >> >> Signed-off-by: Mark Cave-Ayland >> --- >> hw/sparc64/sun4u.c | 17 +++++++++++++---- >> target-sparc/cpu.h | 2 ++ >> 2 files changed, 15 insertions(+), 4 deletions(-) >> >> diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c >> index d6b929c..7153638 100644 >> --- a/hw/sparc64/sun4u.c >> +++ b/hw/sparc64/sun4u.c >> @@ -363,6 +363,8 @@ void cpu_put_timer(QEMUFile *f, CPUTimer *s) >> qemu_put_be32s(f, &s->frequency); >> qemu_put_be32s(f, &s->disabled); >> qemu_put_be64s(f, &s->disabled_mask); >> + qemu_put_be32s(f, &s->npt); >> + qemu_put_be64s(f, &s->npt_mask); >> qemu_put_sbe64s(f, &s->clock_offset); >> >> timer_put(f, s->qtimer); >> @@ -373,6 +375,8 @@ void cpu_get_timer(QEMUFile *f, CPUTimer *s) >> qemu_get_be32s(f, &s->frequency); >> qemu_get_be32s(f, &s->disabled); >> qemu_get_be64s(f, &s->disabled_mask); >> + qemu_get_be32s(f, &s->npt); >> + qemu_get_be64s(f, &s->npt_mask); >> qemu_get_sbe64s(f, &s->clock_offset); >> >> timer_get(f, s->qtimer); > > Hi. I was just rebasing my sparc convert-to-vmstate patchset, and I > noticed this patch due to a conflict. This change breaks migration > and vmstate save/restore compatibility for these boards. > Making the field version-dependent is probably a bit awkward at > this point because these are just subfields in the overall CPU > state and share its version number (which in turn is shared with > the 32-bit CPUs). > > Not sure what you want to do here? Hi Peter, I'm not particularly worried about sun4u for the moment as there are already other reasons why migration would fail, e.g. no VMStateDescription for storing PCI interrupt state in the apb host bridge. Last time I checked sun4m migration appeared to work under some very light testing, so as long as this behaviour is preserved then I don't see a problem. ATB, Mark.