From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJkcr-0007NR-K4 for qemu-devel@nongnu.org; Thu, 14 Jan 2016 11:19:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aJkco-0002dB-Cn for qemu-devel@nongnu.org; Thu, 14 Jan 2016 11:19:53 -0500 Received: from mout.web.de ([212.227.15.4]:57822) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJkco-0002ct-3a for qemu-devel@nongnu.org; Thu, 14 Jan 2016 11:19:50 -0500 References: <1452758668-19284-1-git-send-email-davidkiarie4@gmail.com> <1452758668-19284-4-git-send-email-davidkiarie4@gmail.com> <20160114100946.GA13170@redhat.com> <20160114173824-mutt-send-email-mst@redhat.com> <5697C1F2.109@web.de> From: Jan Kiszka Message-ID: <5697CA9E.7080007@web.de> Date: Thu, 14 Jan 2016 17:19:42 +0100 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="htmwtjo7S3veGlEJuQR3k3WQ7lNH0Gc5b" Subject: Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David kiarie Cc: marcel@redhat.com, Valentine Sinitsyn , Peter Crosthwaite , QEMU Developers , "Michael S. Tsirkin" This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --htmwtjo7S3veGlEJuQR3k3WQ7lNH0Gc5b Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On 2016-01-14 17:09, David kiarie wrote: > On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote: >> On 2016-01-14 16:39, Michael S. Tsirkin wrote: >>> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote: >>>> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin = wrote: >>>>> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote: >>>>>> Add IVRS table for AMD IO MMU. Also reverve MMIO >>>>> >>>>> reserve? >>>> >>>> Yeah, typo. >>>> >>>>> >>>>>> region for IO MMU via ACPI >>>>> >>>>> >>>>> It does not look like you reserve anything. >>>>> >>>>> Pls add a link to hardware spec (in >>>>> the device implementation) so we can check >>>>> what does real hardware do. >>>>> >>>>> If this is it: >>>>> http://developer.amd.com/wordpress/media/2012/10/488821.pdf >>>>> >>>>> then the way that works seems to be by guest >>>>> programming the MMIO base. >>>>> We should do the same: patch seabios and EFI to do this. >>>> >>>> Yes, that's the spec. >>>> >>>> We thought this could be possible via ACPI (without patching BIOS ),= no ? >>> >>> I don't see how. We should do it the way it happens on real hardware.= >>> >> >> Doesn't Seabios retrieve certain ACPI fragments from QEMU via a >> pv-interface by now? >> >> Anyway, the question remains where this address comes from: The BIOS, >> which then writes it into some hw config register and reports it in >> addition via ACPI or the hardware (hard-wired). >=20 > Will look at patching BIOS. Scanning through the spec again: As the address is not hard-wired but configured via registers in the extended capabilities of the corresponding PCI functions of an IOMMU (and also enabled that way!), it's up to the BIOS to allocate an appropriate address for a system. Jan --htmwtjo7S3veGlEJuQR3k3WQ7lNH0Gc5b Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlaXyp4ACgkQitSsb3rl5xT+9ACdHTXpsQ4Rn+33buXnSH5SdL9j sSAAniX7hLp9oL0Yx//0HcmhEWCJCULT =IO1m -----END PGP SIGNATURE----- --htmwtjo7S3veGlEJuQR3k3WQ7lNH0Gc5b--