From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJlZk-0006qc-FZ for qemu-devel@nongnu.org; Thu, 14 Jan 2016 12:20:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aJlZf-0002y6-Bj for qemu-devel@nongnu.org; Thu, 14 Jan 2016 12:20:44 -0500 Received: from mx1.redhat.com ([209.132.183.28]:58149) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJlZe-0002wb-W5 for qemu-devel@nongnu.org; Thu, 14 Jan 2016 12:20:39 -0500 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id 345CAC09FA8F for ; Thu, 14 Jan 2016 17:20:38 +0000 (UTC) References: <5693D447.8070000@redhat.com> <5693D999.2030504@gmail.com> <5693E349.4090201@redhat.com> <5693EE0B.7030002@redhat.com> <5693F802.2010304@redhat.com> <5693FB2F.2080403@redhat.com> <56979399.20902@redhat.com> <5697B111.6070203@redhat.com> <20160114164309-mutt-send-email-mst@redhat.com> <5697BD6F.7030501@redhat.com> <20160114173718-mutt-send-email-mst@redhat.com> From: Marcel Apfelbaum Message-ID: <5697D8E0.7020909@redhat.com> Date: Thu, 14 Jan 2016 19:20:32 +0200 MIME-Version: 1.0 In-Reply-To: <20160114173718-mutt-send-email-mst@redhat.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] hw/pci: do not update the PCI mappings while Decode (I/O or memory) bit is not set in the Command register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Laszlo Ersek , qemu-devel@nongnu.org On 01/14/2016 05:37 PM, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016 at 05:23:27PM +0200, Marcel Apfelbaum wrote: >> On 01/14/2016 04:49 PM, Michael S. Tsirkin wrote: >>> On Thu, Jan 14, 2016 at 03:30:41PM +0100, Laszlo Ersek wrote: >>>>> 2. The same as with pxb, disable Integrated End points for pxb-pcie. >>>> >>>> My vote, without a doubt. >>> >>> Yea, me too. >>> >>> >>> On a related note: I wonder whether enough resources will be allocated >>> to the bridge to actually make it possible to add devices by hotplug >>> later. >>> >> >> It works the same as with PXB, but now instead of having one internal PCI-bridge, >> we will have several switches/root ports. Each of them will get the minimum MEM required by >> PCI bridges, > > what does this mean? What if you add a bunch of devices > with large memory BARs? They won't fit will they? > Indeed, devices with over 1 MB (I think) BARs can't be hot-plugged. This is a known design limitation. We can think of a way to handle this, but the real reason we have multiple root bridges is to be able to correlate an assigned device with a NUMA node. In this case the device will be added more likely at boot time. I think the first step is to have *some* hot-plug support for pxb/pxb-pcie with the current constraints, once it works we can think of a way to make it work for devices with large BARs. Thanks, Marcel >> however the IO will be allocated only if at least one legacy device >> will be present at boot time. (this is at least what SeaBIOS does, I am going to check OVMF actions) >> >> Also related, checking that PCIe native hotplug works for devices behind >> pxb-pcie bridges is my next step after I fix the current issue. >> >> Thanks, >> Marcel >> >>> >>>>> >>>>> I am going to look at 1., maybe I is doable in a clean way. >>>> >>>> My vote: don't. :) >>>> >>>> Thanks >>>> Laszlo >>>> >>>>> Thanks, >>>>> Marcel >>>>> >>>>> >>>>> [...]